8 May 2012, Budapest -- ZTE Corporation announced that Hungarian Minister of Economics, Gy^irgy Matolcsy, and ZTE senior vice president, Zhu Jinyun have signed an agreement to cooperate on the establishment of ZTE＇s ...8 May 2012, Budapest -- ZTE Corporation announced that Hungarian Minister of Economics, Gy^irgy Matolcsy, and ZTE senior vice president, Zhu Jinyun have signed an agreement to cooperate on the establishment of ZTE＇s new European Regional Network Operation Center in Budapest.展开更多
A fully-differential switched-capacitor sample-and-hold （S/H） circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter （ADC） was designed and fabricated using a 0.35-μm CMOS process. Capacitor flip-a...A fully-differential switched-capacitor sample-and-hold （S/H） circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter （ADC） was designed and fabricated using a 0.35-μm CMOS process. Capacitor flip-around architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier （OTA） was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range （SFDR） of 67 dB and a signal-to-noise ratio （SNR） of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12mm^2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.展开更多
文摘8 May 2012, Budapest -- ZTE Corporation announced that Hungarian Minister of Economics, Gy^irgy Matolcsy, and ZTE senior vice president, Zhu Jinyun have signed an agreement to cooperate on the establishment of ZTE＇s new European Regional Network Operation Center in Budapest.
基金supported by the National High Technology Research and Development Program of China(No.2002AA1Z1200)
文摘A fully-differential switched-capacitor sample-and-hold （S/H） circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter （ADC） was designed and fabricated using a 0.35-μm CMOS process. Capacitor flip-around architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier （OTA） was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range （SFDR） of 67 dB and a signal-to-noise ratio （SNR） of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12mm^2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.
