mc211vm is a process-level ARM-to-x86 binary translator developed in our lab in the past several years. Currently, it is able to emulate singlethreaded programs. We extend mc211vm to emulate multi-threaded programs. O...mc211vm is a process-level ARM-to-x86 binary translator developed in our lab in the past several years. Currently, it is able to emulate singlethreaded programs. We extend mc211vm to emulate multi-threaded programs. Our main task is to reconstruct its architecture for multi-threaded programs. Register mapping, code cache management, and address mapping in mc2llvm have all been modified. In addition, to further speed up the emulation, we collect hot paths, aggressively optimize and generate code for them at run time. Additional threads are used to alleviate the overhead. Thus, when the same hot path is walked through again, the corresponding optimized native code will be executed instead. In our experiments, our system is 8.8X faster than QEMU （quick emulator） on average when emulating the specified benchmarks with 8 vip threads.展开更多
A new efficient adapting virtual intermediate instruction set,V-IIS,is designed and implemented towards the optimized dynamic binary translator (DBT) system.With the help of this powerful but previously little-studied...A new efficient adapting virtual intermediate instruction set,V-IIS,is designed and implemented towards the optimized dynamic binary translator (DBT) system.With the help of this powerful but previously little-studied component,DBTs can not only get rid of the dependence of machine(s),but also get better performance.From our systematical study and evaluation,experimental results demonstrate that if V-IIS is well designed,without affecting the other optimizing measures,this could make DBT's performance close to those who do not have intermediate instructions.This study is an important step towards the grand goal of high performance "multi-source" and "multi-target" dynamic binary translation.展开更多
The rapid development of ISAs has brought the issue of software compatibility to the forefront in the embedded field.To address this challenge,one of the promising solutions is the adoption of a multiple-ISA processor...The rapid development of ISAs has brought the issue of software compatibility to the forefront in the embedded field.To address this challenge,one of the promising solutions is the adoption of a multiple-ISA processor that supports multiple different ISAs.However,due to constraints in cost and performance,the architecture of a multiple-ISA processor must be carefully optimized to meet the specific requirements of embedded systems.By exploring the RISC-V and ARM Thumb ISAs,this paper proposes RVAM16,which is an optimized multiple-ISA processor microarchitecture for embedded devices based on hardware binary translation technique.The results show that,when running non-native ARM Thumb programs,RVAM16 achieves a significant speedup of over 2.73×with less area and energy consumption compared to using hardware binary translation alone,reaching more than 70%of the performance of native RISC-V programs.展开更多
Structural relaxation and glass transition in binary hard-spherical particle mixtures have been reported to exhibit unusual features depending on the size disparity and composition. However, the mechanism by which the...Structural relaxation and glass transition in binary hard-spherical particle mixtures have been reported to exhibit unusual features depending on the size disparity and composition. However, the mechanism by which the mixing effects lead to these features and whether these features are universal for particles with anisotropic geometries remains unclear. Here, we employ event-driven molecular dynamics simulation to investigate the dynamical and structural properties of binary two-dimensional hard-ellipse mixtures. We find that the relaxation dynamics for translational degrees of freedom exhibit equivalent trends as those observed in binary hard-spherical mixtures. However, the glass transition densities for translational and rotational degrees of freedom present different dependencies on size disparity and composition. Furthermore,we propose a mechanism based on structural properties that explain the observed mixing effects and decoupling behavior between translational and rotational motions in binary hard-ellipse systems.展开更多
基金supported by NSC under Grant No.NSC 100-2218-E-009-009MY3 and NSC 100-2218-E-009-010-MY3
文摘mc211vm is a process-level ARM-to-x86 binary translator developed in our lab in the past several years. Currently, it is able to emulate singlethreaded programs. We extend mc211vm to emulate multi-threaded programs. Our main task is to reconstruct its architecture for multi-threaded programs. Register mapping, code cache management, and address mapping in mc2llvm have all been modified. In addition, to further speed up the emulation, we collect hot paths, aggressively optimize and generate code for them at run time. Additional threads are used to alleviate the overhead. Thus, when the same hot path is walked through again, the corresponding optimized native code will be executed instead. In our experiments, our system is 8.8X faster than QEMU （quick emulator） on average when emulating the specified benchmarks with 8 vip threads.
基金Projects(12R21414600)supported by Shanghai Municipal Science and Technology Commission,China
文摘A new efficient adapting virtual intermediate instruction set,V-IIS,is designed and implemented towards the optimized dynamic binary translator (DBT) system.With the help of this powerful but previously little-studied component,DBTs can not only get rid of the dependence of machine(s),but also get better performance.From our systematical study and evaluation,experimental results demonstrate that if V-IIS is well designed,without affecting the other optimizing measures,this could make DBT's performance close to those who do not have intermediate instructions.This study is an important step towards the grand goal of high performance "multi-source" and "multi-target" dynamic binary translation.
基金supported in part by the National Natural Science Foundation of China(Grant Nos.62272475,62090023,and 62172430)the National Key R&D Program of China(No.2021YFB0300300)+2 种基金the Natural Science Foundation of Hunan Province of China(Nos.2022JJ10064 and 2021JJ10052)the STIP of Hunan Province(No.2022RC3065)the Key Laboratory of Advanced Microprocessor Chips and Systems.
文摘The rapid development of ISAs has brought the issue of software compatibility to the forefront in the embedded field.To address this challenge,one of the promising solutions is the adoption of a multiple-ISA processor that supports multiple different ISAs.However,due to constraints in cost and performance,the architecture of a multiple-ISA processor must be carefully optimized to meet the specific requirements of embedded systems.By exploring the RISC-V and ARM Thumb ISAs,this paper proposes RVAM16,which is an optimized multiple-ISA processor microarchitecture for embedded devices based on hardware binary translation technique.The results show that,when running non-native ARM Thumb programs,RVAM16 achieves a significant speedup of over 2.73×with less area and energy consumption compared to using hardware binary translation alone,reaching more than 70%of the performance of native RISC-V programs.
基金supported by the National Natural Science Foundation of China(21474109,21674055)the International Partnership Program of Chinese Academy of Sciences(121522KYSB20160015)the Youth Innovation Promotion Association of Chinese Academy of Sciences(2016204)
文摘Structural relaxation and glass transition in binary hard-spherical particle mixtures have been reported to exhibit unusual features depending on the size disparity and composition. However, the mechanism by which the mixing effects lead to these features and whether these features are universal for particles with anisotropic geometries remains unclear. Here, we employ event-driven molecular dynamics simulation to investigate the dynamical and structural properties of binary two-dimensional hard-ellipse mixtures. We find that the relaxation dynamics for translational degrees of freedom exhibit equivalent trends as those observed in binary hard-spherical mixtures. However, the glass transition densities for translational and rotational degrees of freedom present different dependencies on size disparity and composition. Furthermore,we propose a mechanism based on structural properties that explain the observed mixing effects and decoupling behavior between translational and rotational motions in binary hard-ellipse systems.
