为解决标准设计模式演化后难以检测的问题,引入设计模式变体思想,以Bridge模式为例,给出了八种常用的变体实现,并以人工形式挖掘了四种开源系统中Bridge模式变体的基准数,接着在Apache Ant 1.6.2与JHotDraw 5.1开源系统中通过六种主流...为解决标准设计模式演化后难以检测的问题,引入设计模式变体思想,以Bridge模式为例,给出了八种常用的变体实现,并以人工形式挖掘了四种开源系统中Bridge模式变体的基准数,接着在Apache Ant 1.6.2与JHotDraw 5.1开源系统中通过六种主流设计模式检测工具进行了变体检测实验。实验结果表明,FCA-CBR方法简单有效,对两种开源系统中Bridge模式变体检测的精确率达到60%与48.1%,与先前方法相比有了较大的提高。展开更多
Modern shared-memory multi-core processors typically have shared Level 2(L2)or Level 3(L3)caches.Cache bottlenecks and replacement strategies are the main problems of such architectures,where multiple cores try to acc...Modern shared-memory multi-core processors typically have shared Level 2(L2)or Level 3(L3)caches.Cache bottlenecks and replacement strategies are the main problems of such architectures,where multiple cores try to access the shared cache simultaneously.The main problem in improving memory performance is the shared cache architecture and cache replacement.This paper documents the implementation of a Dual-Port Content Addressable Memory(DPCAM)and a modified Near-Far Access Replacement Algorithm(NFRA),which was previously proposed as a shared L2 cache layer in a multi-core processor.Standard Performance Evaluation Corporation(SPEC)Central Processing Unit(CPU)2006 benchmark workloads are used to evaluate the benefit of the shared L2 cache layer.Results show improved performance of the multicore processor’s DPCAM and NFRA algorithms,corresponding to a higher number of concurrent accesses to shared memory.The new architecture significantly increases system throughput and records performance improvements of up to 8.7%on various types of SPEC 2006 benchmarks.The miss rate is also improved by about 13%,with some exceptions in the sphinx3 and bzip2 benchmarks.These results could open a new window for solving the long-standing problems with shared cache in multi-core processors.展开更多
文摘为解决标准设计模式演化后难以检测的问题,引入设计模式变体思想,以Bridge模式为例,给出了八种常用的变体实现,并以人工形式挖掘了四种开源系统中Bridge模式变体的基准数,接着在Apache Ant 1.6.2与JHotDraw 5.1开源系统中通过六种主流设计模式检测工具进行了变体检测实验。实验结果表明,FCA-CBR方法简单有效,对两种开源系统中Bridge模式变体检测的精确率达到60%与48.1%,与先前方法相比有了较大的提高。
文摘Modern shared-memory multi-core processors typically have shared Level 2(L2)or Level 3(L3)caches.Cache bottlenecks and replacement strategies are the main problems of such architectures,where multiple cores try to access the shared cache simultaneously.The main problem in improving memory performance is the shared cache architecture and cache replacement.This paper documents the implementation of a Dual-Port Content Addressable Memory(DPCAM)and a modified Near-Far Access Replacement Algorithm(NFRA),which was previously proposed as a shared L2 cache layer in a multi-core processor.Standard Performance Evaluation Corporation(SPEC)Central Processing Unit(CPU)2006 benchmark workloads are used to evaluate the benefit of the shared L2 cache layer.Results show improved performance of the multicore processor’s DPCAM and NFRA algorithms,corresponding to a higher number of concurrent accesses to shared memory.The new architecture significantly increases system throughput and records performance improvements of up to 8.7%on various types of SPEC 2006 benchmarks.The miss rate is also improved by about 13%,with some exceptions in the sphinx3 and bzip2 benchmarks.These results could open a new window for solving the long-standing problems with shared cache in multi-core processors.
