The mechanism of improving the TID radiation hardened ability of partially depleted silicon-oninsulator（SOI） devices by using the back-gate phosphorus ion implantation technology is studied. The electron traps intro...The mechanism of improving the TID radiation hardened ability of partially depleted silicon-oninsulator（SOI） devices by using the back-gate phosphorus ion implantation technology is studied. The electron traps introduced in Si O2 near back Si O2/Si interface by phosphorus ions implantation can offset positive trapped charges near the back-gate interface. The implanted high concentration phosphorus ions can greatly reduce the back-gate effect of a partially depleted SOI NMOS device, and anti-total-dose radiation ability can reach the level of 1 Mrad（Si） for experimental devices.展开更多
A non-depletion floating layer silicon-on-insulator （NFL SOI） lateral double-diffused metal–oxide–semiconductor （LDMOS） is proposed and the NFL-assisted modulated field （NFLAMF） principle is investigated in th...A non-depletion floating layer silicon-on-insulator （NFL SOI） lateral double-diffused metal–oxide–semiconductor （LDMOS） is proposed and the NFL-assisted modulated field （NFLAMF） principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer （BOX）. At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage （BV） is increased from 315 V to 558 V compared to the conventional reduced surface field （RESURF） SOI （CSOI） LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.展开更多
The hysteresis effect in the output characteristics,originating from the floating body effect,has been measured in partially depleted（PD） silicon-on-insulator（SOI） MOSFETs at different back-gate biases.I D hystere...The hysteresis effect in the output characteristics,originating from the floating body effect,has been measured in partially depleted（PD） silicon-on-insulator（SOI） MOSFETs at different back-gate biases.I D hysteresis has been developed to clarify the hysteresis characteristics.The fabricated devices show the positive and negative peaks in the I D hysteresis.The experimental results show that the I D hysteresis is sensitive to the back gate bias in 0.13-渭m PD SOI MOSFETs and does not vary monotonously with the back-gate bias.Based on the steady-state Shockley-Read-Hall（SRH） recombination theory,we have successfully interpreted the impact of the back-gate bias on the hysteresis effect in PD SOI MOSFETs.展开更多
This paper reports that a novel type of suspended ZnO nanowire field-effect transistors （FETs） were successfully fabricated using a photolithography process, and their electrical properties were characterized by I-V...This paper reports that a novel type of suspended ZnO nanowire field-effect transistors （FETs） were successfully fabricated using a photolithography process, and their electrical properties were characterized by I-V measurements. Single-crystalline ZnO nanowires were synthesized by a hydrothermal method, they were used as a suspended ZnO nanowire channel of back-gate field-effect transistors （FET）. The fabricated suspended nanowire FETs showed a pchannel depletion mode, exhibited high on-off current ratio of -10^5. When VDS = 2.5V, the peak transconductances of the suspended FETs were 0.396 μS, the oxide capacitance was found to be 1.547 fF, the pinch-off voltage VTH was about 0.6 V, the electron mobility was on average 50.17cm2/Vs. The resistivity of the ZnO nanowire channel was estimated to be 0.96 × 10^2 Ω cm at VGS = 0 V. These characteristics revealed that the suspended nanowire FET fabricated by the photolithography process had excellent performance. Better contacts between the ZnO nanowire and metal electrodes could be improved through annealing and metal deposition using a focused ion beam.展开更多
为研究辐照过程中施加背栅偏置对不同沟道长度部分耗尽绝缘体上硅金属氧化物半导体场效应晶体管(Partily Depleted Silicon-On-Insulator Metal Oxide Semiconductor Field Effect Transistors,PD SOI MOSFETs)电参数影响规律,及对隐埋...为研究辐照过程中施加背栅偏置对不同沟道长度部分耗尽绝缘体上硅金属氧化物半导体场效应晶体管(Partily Depleted Silicon-On-Insulator Metal Oxide Semiconductor Field Effect Transistors,PD SOI MOSFETs)电参数影响规律,及对隐埋氧化层(Buried Oxide,BOX)辐射感生陷阱电荷的调控规律及机理。基于晶体管转移特性曲线,通过提取辐射诱导晶体管阈值电压变化量,对比了不同沟道长度PD SOI在不同背栅偏置条件下的辐射损伤数据,试验结果显示:辐照过程中施加背栅偏置可以显著增强长沟晶体管的损伤。通过提取辐射在BOX层中引入陷阱电荷密度,结合TCAD(Technology Computer Aided Design)器件模拟仿真进行了机理研究,研究结果表明:短沟道晶体管在施加背栅偏置时会受到源漏电压的影响,从而使BOX层中电场分布及强度不同于长沟道晶体管,而长沟道晶体管受源漏电压的影响可以忽略。展开更多
The hot-carrier effect charactenstic in a deep submicron partially depleted SOI NMOSFET is investigated. Obvious hot-carrier degradation is observed under off-state stress.The hot-carrier damage is supposed to be indu...The hot-carrier effect charactenstic in a deep submicron partially depleted SOI NMOSFET is investigated. Obvious hot-carrier degradation is observed under off-state stress.The hot-carrier damage is supposed to be induced by the parasitic bipolar effects of a float SOI device.The back channel also suffers degradation from the hot carrier in the drain depletion region as well as the front channel.At low gate voltage,there is a hump in the sub-threshold curve of the back gate transistor,and it does not shift in the same way as the main transistor under stress.While under the same condition,there is a more severe hot-carrier effect with a shorter channel transistor. The reasons for those phenomena are discussed in detail.展开更多
基金Project supported by the Major Fund for the National Science and Technology Program,China(No.2009ZX02306-04)the Fund of SOI Research and Development Center(No.20106250XXX)
文摘The mechanism of improving the TID radiation hardened ability of partially depleted silicon-oninsulator（SOI） devices by using the back-gate phosphorus ion implantation technology is studied. The electron traps introduced in Si O2 near back Si O2/Si interface by phosphorus ions implantation can offset positive trapped charges near the back-gate interface. The implanted high concentration phosphorus ions can greatly reduce the back-gate effect of a partially depleted SOI NMOS device, and anti-total-dose radiation ability can reach the level of 1 Mrad（Si） for experimental devices.
文摘A non-depletion floating layer silicon-on-insulator （NFL SOI） lateral double-diffused metal–oxide–semiconductor （LDMOS） is proposed and the NFL-assisted modulated field （NFLAMF） principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer （BOX）. At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage （BV） is increased from 315 V to 558 V compared to the conventional reduced surface field （RESURF） SOI （CSOI） LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.
基金Project supported by the TCAD Simulation and SPICE Modeling of 0.13μm SOI Technology,China (Grant No. 2009ZX02306-002)
文摘The hysteresis effect in the output characteristics,originating from the floating body effect,has been measured in partially depleted（PD） silicon-on-insulator（SOI） MOSFETs at different back-gate biases.I D hysteresis has been developed to clarify the hysteresis characteristics.The fabricated devices show the positive and negative peaks in the I D hysteresis.The experimental results show that the I D hysteresis is sensitive to the back gate bias in 0.13-渭m PD SOI MOSFETs and does not vary monotonously with the back-gate bias.Based on the steady-state Shockley-Read-Hall（SRH） recombination theory,we have successfully interpreted the impact of the back-gate bias on the hysteresis effect in PD SOI MOSFETs.
文摘This paper reports that a novel type of suspended ZnO nanowire field-effect transistors （FETs） were successfully fabricated using a photolithography process, and their electrical properties were characterized by I-V measurements. Single-crystalline ZnO nanowires were synthesized by a hydrothermal method, they were used as a suspended ZnO nanowire channel of back-gate field-effect transistors （FET）. The fabricated suspended nanowire FETs showed a pchannel depletion mode, exhibited high on-off current ratio of -10^5. When VDS = 2.5V, the peak transconductances of the suspended FETs were 0.396 μS, the oxide capacitance was found to be 1.547 fF, the pinch-off voltage VTH was about 0.6 V, the electron mobility was on average 50.17cm2/Vs. The resistivity of the ZnO nanowire channel was estimated to be 0.96 × 10^2 Ω cm at VGS = 0 V. These characteristics revealed that the suspended nanowire FET fabricated by the photolithography process had excellent performance. Better contacts between the ZnO nanowire and metal electrodes could be improved through annealing and metal deposition using a focused ion beam.
文摘The hot-carrier effect charactenstic in a deep submicron partially depleted SOI NMOSFET is investigated. Obvious hot-carrier degradation is observed under off-state stress.The hot-carrier damage is supposed to be induced by the parasitic bipolar effects of a float SOI device.The back channel also suffers degradation from the hot carrier in the drain depletion region as well as the front channel.At low gate voltage,there is a hump in the sub-threshold curve of the back gate transistor,and it does not shift in the same way as the main transistor under stress.While under the same condition,there is a more severe hot-carrier effect with a shorter channel transistor. The reasons for those phenomena are discussed in detail.
