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Probability gate model based methods for approximate arithmetic circuits reliability estimation
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作者 Jianhui Jiang Tao Wang Zhen Wang 《CCF Transactions on High Performance Computing》 2021年第2期201-219,共19页
With the rapid development of approximate computing technology, the reliability evaluation of approximate circuits hasattracted significant interest. So far, few methods can be applied to estimate the reliability of a... With the rapid development of approximate computing technology, the reliability evaluation of approximate circuits hasattracted significant interest. So far, few methods can be applied to estimate the reliability of approximate circuits, the existingmethods are based on probability transfer module (PTM) and Monte Carlo (MC) method. However, the PTM-basedmethods are confined to small-scale approximate circuits and large circuits with weak signal correlation, and the MC methodis time-consuming to obtain accurate results. This paper proposes an algorithm for determining the acceptable outputs ofapproximate dividers based on the design principle of the approximate divider. Then based on the probability gate model(PGM), this paper presents three methods for reliability estimation of gate-level approximate arithmetic circuits. The nonprocessingcorrelation algorithm does not consider the correlation among signals to obtain an approximate value of circuitreliability, and its time complexity keeps a linear relation with the number of gates. The processing correlation algorithm canestimate the correlation caused by fanout nodes of the approximate arithmetic circuits, and it has the obvious advantage onaccuracy. However, its time complexity is exponential with the number of fanout nodes in the circuit. The fusion algorithmconsiders the effect of each fanout node on the reliability of the circuit separately and then uses a linear model to obtain thecircuit reliability. Although some accuracy is lost, the time complexity is linear. The experimental results on benchmarkcircuits show that the proposed methods are effective, and have certain advantages in accuracy and efficiency as comparedwith the existing methods. 展开更多
关键词 Reliability estimation Probabilistic gate model Approximate arithmetic circuit circuit acceptable output
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Comparison of dynamic Bayesian network approaches for online diagnosis of aircraft system 被引量:2
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作者 于劲松 冯威 +1 位作者 唐荻音 刘浩 《Journal of Central South University》 SCIE EI CAS CSCD 2016年第11期2926-2934,共9页
The online diagnosis for aircraft system has always been a difficult problem. This is due to time evolution of system change, uncertainty of sensor measurements, and real-time requirement of diagnostic inference. To a... The online diagnosis for aircraft system has always been a difficult problem. This is due to time evolution of system change, uncertainty of sensor measurements, and real-time requirement of diagnostic inference. To address this problem, two dynamic Bayesian network(DBN) approaches are proposed. One approach prunes the DBN of system, and then uses particle filter(PF) for this pruned DBN(PDBN) to perform online diagnosis. The problem is that estimates from a PF tend to have high variance for small sample sets. Using large sample sets is computationally expensive. The other approach compiles the PDBN into a dynamic arithmetic circuit(DAC) using an offline procedure that is applied only once, and then uses this circuit to provide online diagnosis recursively. This approach leads to the most computational consumption in the offline procedure. The experimental results show that the DAC, compared with the PF for PDBN, not only provides more reliable online diagnosis, but also offers much faster inference. 展开更多
关键词 online diagnosis dynamic Bayesian network particle filter dynamic arithmetic circuit
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Arithmetic Operand Ordering for Equivalence Checking
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作者 翁延玲 葛海通 +1 位作者 严晓浪 任坤 《Tsinghua Science and Technology》 SCIE EI CAS 2007年第S1期235-239,共5页
An information extraction-based technique is proposed for RTL-to-gate equivalence checking. Distances are calculated on directed acyclic graph (AIG). Multiplier and multiplicand are distinguished on multiplications wi... An information extraction-based technique is proposed for RTL-to-gate equivalence checking. Distances are calculated on directed acyclic graph (AIG). Multiplier and multiplicand are distinguished on multiplications with different coding methods, with which the operand ordering/grouping information could be extracted from a given implementation gate netlist, helping the RTL synthesis engine generate a gate netlist with great similarity. This technique has been implemented in an internal equivalence checking tool, ZDIS. Compared with the simple equivalence checking, the speed is accelerated by at least 40% in its application to a class of arithmetic designs, addition and multiplication trees. The method can be easily incorporated into existing RTL-to-gate equivalence checking frameworks, increasing the robustness of equivalence checking for arithmetic circuits. 展开更多
关键词 SYNTHESIS equivalence checking arithmetic circuit
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