By applying a result from geometric Goppa codes, due to H.Schtenoth, the true dimension of certain alternant codes is calculated. The results lead in many cases to an improvement of the usual lower bound for the dimen...By applying a result from geometric Goppa codes, due to H.Schtenoth, the true dimension of certain alternant codes is calculated. The results lead in many cases to an improvement of the usual lower bound for the dimension.展开更多
This paper presents a new test data compression/decompression method for SoC testing,called hybrid run length codes. The method makes a full analysis of the factors which influence test parameters：compression ratio,t...This paper presents a new test data compression/decompression method for SoC testing,called hybrid run length codes. The method makes a full analysis of the factors which influence test parameters：compression ratio,test application time, and area overhead. To improve the compression ratio, the new method is based on variable-to-variable run length codes,and a novel algorithm is proposed to reorder the test vectors and fill the unspecified bits in the pre-processing step. With a novel on-chip decoder, low test application time and low area overhead are obtained by hybrid run length codes. Finally, an experimental comparison on ISCAS 89 benchmark circuits validates the proposed method展开更多
Decoding by alternating direction method of multipliers(ADMM) is a promising linear programming decoder for low-density parity-check(LDPC) codes. In this paper, we propose a two-step scheme to lower the error floor of...Decoding by alternating direction method of multipliers(ADMM) is a promising linear programming decoder for low-density parity-check(LDPC) codes. In this paper, we propose a two-step scheme to lower the error floor of LDPC codes with ADMM penalized decoder.For the undetected errors that cannot be avoided at the decoder side, we modify the code structure slightly to eliminate low-weight code words. For the detected errors induced by small error-prone structures, we propose a post-processing method for the ADMM penalized decoder. Simulation results show that the error floor can be reduced significantly over three illustrated LDPC codes by the proposed two-step scheme.展开更多
In this paper, fatigue verification of Class 1 nuclear power piping according to ASME Boiler ＆ Pressure Vessel Code, Section III, NB-3600, is addressed. Basic design requirements and relevant verification procedures ...In this paper, fatigue verification of Class 1 nuclear power piping according to ASME Boiler ＆ Pressure Vessel Code, Section III, NB-3600, is addressed. Basic design requirements and relevant verification procedures using Design-By-Analysis are first reviewed in detail. Thereafter, a so-called simplified elastic-plastic discontinuity analysis for further verification when the basic requirements found unsatisfactory is examined and discussed. In addition, necessary computational procedures for evaluating alternating stress intensities and cumulative damage factors are studied in detail. The authors＇ emphasis is placed on alternative verification procedures, which do not violate the general design principles upon which the code is built, for further verification if unsatisfactory results are found in the simplified elastic-plastic analysis. An alternative which employs a non-linear finite element computation and a refined numerical approach for re-evaluating the cumulative damage factors is suggested. Using this alternative, unavoidable plastic strains can be correctly taken into account in a computationally affordable way, and the reliability of the verification will not be affected by uncertainties introduced in the simplified elastic-plastic analysis through the penalty factor Ke and other simplifications.展开更多
The test vector compression is a key technique to reduce IC test time and cost since the explosion of the test data of system on chip （SoC） in recent years. To reduce the bandwidth requirement between the automatic ...The test vector compression is a key technique to reduce IC test time and cost since the explosion of the test data of system on chip （SoC） in recent years. To reduce the bandwidth requirement between the automatic test equipment （ATE） and the CUT （circuit under test） effectively, a novel VSPTIDR （variable shifting prefix-tail identifier reverse） code for test stimulus data compression is designed. The encoding scheme is defined and analyzed in detail, and the decoder is presented and discussed. While the probability of 0 bits in the test set is greater than 0.92, the compression ratio from VSPTIDR code is better than the frequency-directed run-length （FDR） code, which can be proved by theoretical analysis and experiments. And the on-chip area overhead of VSPTIDR decoder is about 15.75 % less than the FDR decoder.展开更多
针对现有抗噪声调频干扰相位编码波形设计算法存在计算复杂度高、难以满足实时处理需求的问题,本文提出了一种基于频域坐标下降的高效优化算法。首先,将时域联合优化目标函数转换至频域,建立相位编码波形的频域优化模型。该转换不仅有...针对现有抗噪声调频干扰相位编码波形设计算法存在计算复杂度高、难以满足实时处理需求的问题,本文提出了一种基于频域坐标下降的高效优化算法。首先,将时域联合优化目标函数转换至频域,建立相位编码波形的频域优化模型。该转换不仅有效规避了时域优化过程中大规模矩阵运算带来的高计算代价,还使得优化问题结构更为简洁,便于后续的算法设计。随后,在交替方向乘子法(Alternating Direction Method of Multipliers,ADMM)框架下引入频域坐标下降法(Frequency-domain Coordinate Descent Method,FCDM),形成了ADMMFCDM算法。该算法将复杂的高维优化问题分解为多个可独立并行处理的一维子问题,通过推导波形频域序列元素的闭式解,不仅大幅降低了单次迭代的计算量,还显著提升了全局优化效率。最后,本文引入快速傅里叶变换(Fast Fourier Transform,FFT)技术对ADMM-FCDM进行简化,得到了交替方向乘子法框架下结合快速傅里叶变换的频域坐标下降算法(Frequency-domain Coordinate Descent Method with Fast Fourier Transform under Alternating Direction Method of Multipliers Framework,ADMM-FFT-FCDM)。FFT的引入极大程度地降低了时域与频域之间变换所需的计算时间,进一步提升了算法的运算效率。仿真实验表明,较于现有算法,本文提出的ADMM-FFTFCDM算法在保证雷达抗干扰性能和探测性能的同时,运算速度获得显著提升。展开更多
基金Supported by the National Natural Science Foundation of China(No.69872016)
文摘By applying a result from geometric Goppa codes, due to H.Schtenoth, the true dimension of certain alternant codes is calculated. The results lead in many cases to an improvement of the usual lower bound for the dimension.
文摘This paper presents a new test data compression/decompression method for SoC testing,called hybrid run length codes. The method makes a full analysis of the factors which influence test parameters：compression ratio,test application time, and area overhead. To improve the compression ratio, the new method is based on variable-to-variable run length codes,and a novel algorithm is proposed to reorder the test vectors and fill the unspecified bits in the pre-processing step. With a novel on-chip decoder, low test application time and low area overhead are obtained by hybrid run length codes. Finally, an experimental comparison on ISCAS 89 benchmark circuits validates the proposed method
基金supported in part by National Nature Science Foundation of China under Grant No.61471286,No.61271004the Fundamental Research Funds for the Central Universitiesthe open research fund of Key Laboratory of Information Coding and Transmission,Southwest Jiaotong University(No.2010-03)
文摘Decoding by alternating direction method of multipliers(ADMM) is a promising linear programming decoder for low-density parity-check(LDPC) codes. In this paper, we propose a two-step scheme to lower the error floor of LDPC codes with ADMM penalized decoder.For the undetected errors that cannot be avoided at the decoder side, we modify the code structure slightly to eliminate low-weight code words. For the detected errors induced by small error-prone structures, we propose a post-processing method for the ADMM penalized decoder. Simulation results show that the error floor can be reduced significantly over three illustrated LDPC codes by the proposed two-step scheme.
文摘In this paper, fatigue verification of Class 1 nuclear power piping according to ASME Boiler ＆ Pressure Vessel Code, Section III, NB-3600, is addressed. Basic design requirements and relevant verification procedures using Design-By-Analysis are first reviewed in detail. Thereafter, a so-called simplified elastic-plastic discontinuity analysis for further verification when the basic requirements found unsatisfactory is examined and discussed. In addition, necessary computational procedures for evaluating alternating stress intensities and cumulative damage factors are studied in detail. The authors＇ emphasis is placed on alternative verification procedures, which do not violate the general design principles upon which the code is built, for further verification if unsatisfactory results are found in the simplified elastic-plastic analysis. An alternative which employs a non-linear finite element computation and a refined numerical approach for re-evaluating the cumulative damage factors is suggested. Using this alternative, unavoidable plastic strains can be correctly taken into account in a computationally affordable way, and the reliability of the verification will not be affected by uncertainties introduced in the simplified elastic-plastic analysis through the penalty factor Ke and other simplifications.
基金supported by the Shenzhen Government R&D Project under Grant No.JC200903160361A
文摘The test vector compression is a key technique to reduce IC test time and cost since the explosion of the test data of system on chip （SoC） in recent years. To reduce the bandwidth requirement between the automatic test equipment （ATE） and the CUT （circuit under test） effectively, a novel VSPTIDR （variable shifting prefix-tail identifier reverse） code for test stimulus data compression is designed. The encoding scheme is defined and analyzed in detail, and the decoder is presented and discussed. While the probability of 0 bits in the test set is greater than 0.92, the compression ratio from VSPTIDR code is better than the frequency-directed run-length （FDR） code, which can be proved by theoretical analysis and experiments. And the on-chip area overhead of VSPTIDR decoder is about 15.75 % less than the FDR decoder.
文摘针对具有星间链路(inter-satellite links,ISL)的低轨(low earth orbit,LEO)多卫星系统,提出了一种基于多卫星协作传输的和速率(sum rate,SR)最大化预编码算法.传统的预编码算法需要复杂的星上计算来得到数值解,这导致低轨卫星系统面临较大的计算开销和延迟问题.为解决上述关键问题,设计了一种基于交替方向乘子法(alternating direction method of multipliers,ADMM)的高吞吐量、低复杂度、具有闭式解的分布式预编码算法.该算法通过构建辅助变量和问题分解,将预编码设计问题转化为多个子问题并行求解,每个子问题仅有一个约束条件,并在每次迭代后仅通过星间链路交换设计的数据矩阵,从而有效实现分布式预编码.仿真结果表明,与典型的两步和速率最大化算法相比,所提出的算法可以实现更高的和速率,同时大幅降低计算复杂度.
文摘针对现有抗噪声调频干扰相位编码波形设计算法存在计算复杂度高、难以满足实时处理需求的问题,本文提出了一种基于频域坐标下降的高效优化算法。首先,将时域联合优化目标函数转换至频域,建立相位编码波形的频域优化模型。该转换不仅有效规避了时域优化过程中大规模矩阵运算带来的高计算代价,还使得优化问题结构更为简洁,便于后续的算法设计。随后,在交替方向乘子法(Alternating Direction Method of Multipliers,ADMM)框架下引入频域坐标下降法(Frequency-domain Coordinate Descent Method,FCDM),形成了ADMMFCDM算法。该算法将复杂的高维优化问题分解为多个可独立并行处理的一维子问题,通过推导波形频域序列元素的闭式解,不仅大幅降低了单次迭代的计算量,还显著提升了全局优化效率。最后,本文引入快速傅里叶变换(Fast Fourier Transform,FFT)技术对ADMM-FCDM进行简化,得到了交替方向乘子法框架下结合快速傅里叶变换的频域坐标下降算法(Frequency-domain Coordinate Descent Method with Fast Fourier Transform under Alternating Direction Method of Multipliers Framework,ADMM-FFT-FCDM)。FFT的引入极大程度地降低了时域与频域之间变换所需的计算时间,进一步提升了算法的运算效率。仿真实验表明,较于现有算法,本文提出的ADMM-FFTFCDM算法在保证雷达抗干扰性能和探测性能的同时,运算速度获得显著提升。
