In order to investigate the injection current uniformity around the induction cell bores, two fully electromagnetic （EM） models are respectively established for a single-stage induction cell and an induction voltage...In order to investigate the injection current uniformity around the induction cell bores, two fully electromagnetic （EM） models are respectively established for a single-stage induction cell and an induction voltage adder （IVA） with three cells stacked in series, without considering electron emission. By means of these two models, some factors affecting the injection current uni- formity are simulated and analyzed, such as the impedances of adders and loads, cell locations, and feed timing of parallel driving pulses. Simulation results indicate that higher impedances of adder and loads are slightly beneficial to improve injection current uniformity. As the impedances of adder and loads increase from 5 Ω to 30Ω, the asymmetric coefficient of feed currents decreases from 10.3% to 6.6%. The current non-uniformity within the first cell is a little worse than that in other downstream cells. Simulation results also show that the feed timing would greatly affect current waveforms, and consequently cause some distortion in pulse fronts of cell output voltages. For a given driving pulse with duration time of 70-80 ns, the feed timing with a time deviation of less than 20 ns is acceptable for the three-cell IVAs, just causing the rise time of output voltages to increase about 5 ns at most and making the peak voltage decrease by 3.5%.展开更多
Low power adder circuits, SERF, 10T Ⅰ,10T Ⅱ,10T Ⅲ and a complementary adder (28T) at physical layout level are evaluated. Simulations based on the extracted adder circuit layouts are run to assess how various circu...Low power adder circuits, SERF, 10T Ⅰ,10T Ⅱ,10T Ⅲ and a complementary adder (28T) at physical layout level are evaluated. Simulations based on the extracted adder circuit layouts are run to assess how various circuit setups can impact the speed and power consumption. In addition, impacts of output inverters on the circuit performance of modified SERF and 10T adders due to threshold loss problem are also examined. Differences among these adders are addressed and applications of these adders are suggested.展开更多
Decimal arithmetic is desirable for high precision requirements of many financial, industrial and scientific applications. Furthermore, hardware support for decimal arithmetic has gained momentum with IEEE 754-2008, w...Decimal arithmetic is desirable for high precision requirements of many financial, industrial and scientific applications. Furthermore, hardware support for decimal arithmetic has gained momentum with IEEE 754-2008, which standardized decimal floating-point. This paper presents a new architecture for two operand and multi-operand signed-digit decimal addition. Signed-digit architectures are advantageous because there are no carry-propagate chains. The proposed signed-digit adder reduces the critical path delay by parallelizing the correction stage inherent to decimal addition. For performance evaluation, we synthesize and compare multiple unsigned and signed-digit multi-operand decimal adder architectures on 0.18μm CMOS VLSI technology. Synthesis results for 2, 4, 8, and 16 operands with 8 decimal digits provide critical data in determining each adder's performance and scalability.展开更多
The advent of Grover’s algorithm presents a significant threat to classical block cipher security,spurring research into post-quantum secure cipher design.This study engineers quantum circuit implementations for thre...The advent of Grover’s algorithm presents a significant threat to classical block cipher security,spurring research into post-quantum secure cipher design.This study engineers quantum circuit implementations for three versions of the Ballet family block ciphers.The Ballet‑p/k includes a modular-addition operation uncommon in lightweight block ciphers.Quantum ripple-carry adder is implemented for both“32+32”and“64+64”scale to support this operation.Subsequently,qubits,quantum gates count,and quantum circuit depth of three versions of Ballet algorithm are systematically evaluated under quantum computing model,and key recovery attack circuits are constructed based on Grover’s algorithm against each version.The comprehensive analysis shows:Ballet-128/128 fails to NIST Level 1 security,while when the resource accounting is restricted to the Clifford gates and T gates set for the Ballet-128/256 and Ballet-256/256 quantum circuits,the design attains Level 3.展开更多
Designing logic circuits using complementary metal-oxide-semiconductor(CMOS)technology at the nano scale has been faced with various challenges recently.Undesirable leakage currents,the short-effect channel,and high e...Designing logic circuits using complementary metal-oxide-semiconductor(CMOS)technology at the nano scale has been faced with various challenges recently.Undesirable leakage currents,the short-effect channel,and high energy dissipation are some of the concerns.Quantum-dot cellular automata(QCA)represent an appropriate alternative for possible CMOS replacement in the future because it consumes an insignificant amount of energy compared to the standard CMOS.The key point of designing arithmetic circuits is based on the structure of a 1-bit full adder.A low-complexity full adder block is beneficial for developing various intricate structures.This paper represents scalable 1-bit QCA full adder structures based on cell interaction.Our proposed full adders encompass preference aspects of QCA design,such as a low number of cells used,low latency,and small area occupation.Also,the proposed structures have been expanded to larger circuits,including a 4-bit ripple carry adder(RCA),a 4-bit ripple borrow subtractor(RBS),an add/sub circuit,and a 2-bit array multiplier.All designs were simulated and verified using QCA Designer-E version 2.2.This tool can estimate the energy dissipation as well as evaluate the performance of the circuits.Simulation results showed that the proposed designs are efficient in complexity,area,latency,cost,and energy dissipation.展开更多
Decimal arithmetic circuits are promising to provide a solution for accurate decimal arithmetic operations which are not possible with binary arithmetic circuits.They can be used in banking,commercial and financial tr...Decimal arithmetic circuits are promising to provide a solution for accurate decimal arithmetic operations which are not possible with binary arithmetic circuits.They can be used in banking,commercial and financial transactions,scientific measurements,etc.This article presents the Very Large Scale Integration(VLSI)design of Binary Coded Decimal(BCD)-4221 area-optimized adder architecture using unconventional BCD-4221 representation.Unconventional BCD number representations such as BCD4221 also possess the additional advantage of more effectively representing the 10's complement representation which can be used to accelerate the decimal arithmetic operations.The design uses a binary Carry Lookahead Adder(CLA)along with some other logic blocks which are required to perform internal calculations with BCD-4221 numbers.The design is verified by using Xilinx Vivado 2016.1.Synthesis results have been obtained by Cadence Genus16.1 synthesis tool using 90 nm technology.The performance parameters such as area,power,delay,and area-delay Product(ADP)are compared with earlier reported circuits.Our proposed circuit shows significant area and ADP improvement over existing designs.展开更多
This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFETbased ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability o...This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFETbased ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characteristics of CNTFETs make them very suitable for designing high-performance multiple-Vth structures. The proposed structures reduce the number of the transistors considerably and have very high driving capability. The presented ternary Full Adders are simulated using Synopsys HSPICE with 32 nm CNTFET technology to evaluate their performance and to confirm their correct operation.展开更多
New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study o...New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.展开更多
在现有全加器研究基础上,提出一种高性能全加器改进电路(improved full adder circuit,IFAC),通过改进全加器电路结构,优化电路元件工作数量,旨在提升加法器逻辑功能与运行状态。采用Candence软件搭载130 nm芯片锻造工艺,引入欧拉路径...在现有全加器研究基础上,提出一种高性能全加器改进电路(improved full adder circuit,IFAC),通过改进全加器电路结构,优化电路元件工作数量,旨在提升加法器逻辑功能与运行状态。采用Candence软件搭载130 nm芯片锻造工艺,引入欧拉路径快速判寻法设计其电路版图,验证版图规则的合理性,并利用版图验证工具Dracula对电路进行仿真测试,结果表明本文所设计的全加器较常规全加器在处理复杂网络精确度、传输延迟时间、低功耗稳定运行及芯片面积方面有所提升。展开更多
Skyrmion-based devices are promising candi-dates for non-volatile memory and low-delay time com-putation.Many skyrmion-based devices execute operation by controlling skyrmion trajectory,which can be impeded by the sky...Skyrmion-based devices are promising candi-dates for non-volatile memory and low-delay time com-putation.Many skyrmion-based devices execute operation by controlling skyrmion trajectory,which can be impeded by the skyrmion Hall effect.Here,the design of skyrmion-based arithmetic devices built on synthetic antiferromag-netic(SyAF)structures is presented,where the structure can greatly suppress skyrmion Hall effect.In this study,the operations of skyrmion-based half adder,full adder,and XOR logic gate are executed by introducing geometric notches and tilted edges,which can annihilate or diverge skyrmion.Performance of these skyrmion-based devices is evaluated,where the delay time and energy-delay product of the single-bit full adder are 1.95 ns and 2.50×10^(-22)Js,which are only 12%and 79%those of the previously proposed skyrmion-based single-bit full adder.This improvement is significant in the construction of ripple-carry adder and ripple-carry adder-subtractor.Therefore,our skyrmion-based SyAF arithmetic device is a promising candidate to develop high-speed spintronic devices.展开更多
The design of a three-input logic circuit using carbon nanotube field effect transistors(CNTFETs)is presented.Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital de...The design of a three-input logic circuit using carbon nanotube field effect transistors(CNTFETs)is presented.Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital devices,which is why this design is so popular,and it also reduces chip area,both of which are examples of circuit overheads.The proposed module we have investigated is a triple-logic-based one,based on advanced technology CNTFETs and an emphasis on minimizing delay times at various values,as well as comparisons of the design working with various load capacitances.Comparing the proposed design with the existing design,the delay times was reduced from 66.32 to 16.41 ps,i.e.,a 75.26%reduction.However,the power dissipation was not optimized,and increased by 1.44%compared to the existing adder.The number of transistors was also reduced,and the product of power and delay(P∗D)achieved a value of 0.0498053 fJ.An improvement at 1 V was also achieved.A load capacitance(fF)was measured at different values,and the average delay measured for different values of capacitance had a maximum of 83.60 ps and a minimum of 22.54 ps,with a range of 61.06 ps.The power dissipations ranged from a minimum of 3.38μW to a maximum of 6.49μW.Based on these results,the use of this CNTFET half-adder design in multiple Boolean circuits will be a useful addition to circuit design.展开更多
Compared with a sinusoidal operation, pulsed operation has more homogeneity and more efficiency in dielectric barrier discharge. In this paper, an improved pulse adder is designed and assembled to create repetitive hi...Compared with a sinusoidal operation, pulsed operation has more homogeneity and more efficiency in dielectric barrier discharge. In this paper, an improved pulse adder is designed and assembled to create repetitive high voltage rectangular pulses when resistive loads or capacitive loads exist. Beyond the normal pulse adder based on solid-state switches, additional metal- oxide-semiconductor field effect transistors are used in each stage for a faster falling edge. Further, the voltage difference between stages is eliminated by balancing windings. In this paper, we represent our theoretical derivation, software simulations and hardware experiments on magnetic self-balance. The experiments show that the voltage difference between stages is eliminated by balancing windings, which matches the result of simulations with almost identical circuits and parameters.展开更多
The adders are the vital arithmetic operation for any arithmetic operations like multiplication,subtraction,and division.Binary number additions are performed by the digital circuit known as the adder.In VLSI(Very Lar...The adders are the vital arithmetic operation for any arithmetic operations like multiplication,subtraction,and division.Binary number additions are performed by the digital circuit known as the adder.In VLSI(Very Large Scale Integration),the full adder is a basic component as it plays a major role in designing the integrated circuits applications.To minimize the power,various adder designs are implemented and each implemented designs undergo defined drawbacks.The designed adder requires high power when the driving capability is perfect and requires low power when the delay occurred is more.To overcome such issues and to obtain better performance,a novel parallel adder is proposed.The design of adder is initiated with 1 bit and has been extended up to 32 bits so as verify its scalability.This proposed novel parallel adder is attained from the carry look-ahead adder.The merits of this suggested adder are better speed,power consumption and delay,and the capability in driving.Thus designed adders are verified for different supply,delay,power,leakage and its performance is found to be superior to competitive Manchester Carry Chain Adder(MCCA),Carry Look Ahead Adder(CLAA),Carry Select Adder(CSLA),Carry Select Adder(CSA)and other adders.展开更多
12001 Transformational Logic of Numbers of PurseEquivalence and its Error. Xiao Mingyao: 1(3). 1980pp 190--197Multiplier or counter --type adder can be usually used torealize the multiplication of two multidigit figur...12001 Transformational Logic of Numbers of PurseEquivalence and its Error. Xiao Mingyao: 1(3). 1980pp 190--197Multiplier or counter --type adder can be usually used torealize the multiplication of two multidigit figures. Thispaper Introduces a Simple method, namely. the展开更多
How cells accomplish cell size homeostasis is a fascinating topic, and several cell size regulation mechanisms were proposed: timer, sizer, and adder. Recently the adder model has received a great deal of attention. A...How cells accomplish cell size homeostasis is a fascinating topic, and several cell size regulation mechanisms were proposed: timer, sizer, and adder. Recently the adder model has received a great deal of attention. Adder property was also found in the DNA replication cycle. This paper aims to explain the adder phenomenon both in the division-centric picture and replication-centric picture at the molecular level. We established a self-replication model, and the system reached a steady state quickly based on evolution rules. We collected tens of thousands of cells in the same trajectory and calculated the Pearson correlation coefficient between biological variables to decide which regulatory mechanism was adopted by cells. Our simulation results confirmed the double-adder mechanism. Chromosome replication initiation and cell division control are independent and regulated by respective proteins.Cell size homeostasis originates from division control and has nothing to do with replication initiation control. At a slow growth rate, the deviation from adder toward sizer comes from a significant division protein degradation rate when division protein is auto-inhibited. Our results indicated the two necessary conditions in the double-adder mechanism: one is balanced biosynthesis, and the other is that there is a protein trigger threshold to inspire DNA replication initiation and cell division. Our results give insight to the regulatory mechanism of cell size and instructive to synthetic biology.展开更多
Due to the demand of high computational speed for processing big data that requires complex data manipulations in a timely manner,the need for extending classical logic to construct new multi-valued optical models bec...Due to the demand of high computational speed for processing big data that requires complex data manipulations in a timely manner,the need for extending classical logic to construct new multi-valued optical models becomes a challenging and promising research area.This paper establishes a novel octal-valued logic design model with new optical gates construction based on the hypothesis of Light Color State Model to provide an efficient solution to the limitations of computational processing inherent in the electronics computing.We provide new mathematical definitions for both of the binary OR function and the PLUS operation in multi valued logic that is used as the basis of novel construction for the optical full adder model.Four case studies were used to assure the validity of the proposed adder.These cases proved that the proposed optical 8-valued logic models provide significantly more information to be packed within a single bit and therefore the abilities of data representation and processing is increased.展开更多
基金supported by National Natural Science Foundation of China(No.51307141)partly by the State Key Laboratory of Intense Pulsed Radiation Simulation(Northwest Institute of Nuclear Technology)under Contract SKLIPR 1206
文摘In order to investigate the injection current uniformity around the induction cell bores, two fully electromagnetic （EM） models are respectively established for a single-stage induction cell and an induction voltage adder （IVA） with three cells stacked in series, without considering electron emission. By means of these two models, some factors affecting the injection current uni- formity are simulated and analyzed, such as the impedances of adders and loads, cell locations, and feed timing of parallel driving pulses. Simulation results indicate that higher impedances of adder and loads are slightly beneficial to improve injection current uniformity. As the impedances of adder and loads increase from 5 Ω to 30Ω, the asymmetric coefficient of feed currents decreases from 10.3% to 6.6%. The current non-uniformity within the first cell is a little worse than that in other downstream cells. Simulation results also show that the feed timing would greatly affect current waveforms, and consequently cause some distortion in pulse fronts of cell output voltages. For a given driving pulse with duration time of 70-80 ns, the feed timing with a time deviation of less than 20 ns is acceptable for the three-cell IVAs, just causing the rise time of output voltages to increase about 5 ns at most and making the peak voltage decrease by 3.5%.
文摘Low power adder circuits, SERF, 10T Ⅰ,10T Ⅱ,10T Ⅲ and a complementary adder (28T) at physical layout level are evaluated. Simulations based on the extracted adder circuit layouts are run to assess how various circuit setups can impact the speed and power consumption. In addition, impacts of output inverters on the circuit performance of modified SERF and 10T adders due to threshold loss problem are also examined. Differences among these adders are addressed and applications of these adders are suggested.
文摘Decimal arithmetic is desirable for high precision requirements of many financial, industrial and scientific applications. Furthermore, hardware support for decimal arithmetic has gained momentum with IEEE 754-2008, which standardized decimal floating-point. This paper presents a new architecture for two operand and multi-operand signed-digit decimal addition. Signed-digit architectures are advantageous because there are no carry-propagate chains. The proposed signed-digit adder reduces the critical path delay by parallelizing the correction stage inherent to decimal addition. For performance evaluation, we synthesize and compare multiple unsigned and signed-digit multi-operand decimal adder architectures on 0.18μm CMOS VLSI technology. Synthesis results for 2, 4, 8, and 16 operands with 8 decimal digits provide critical data in determining each adder's performance and scalability.
基金State Key Lab of Processors,Institute of Computing Technology,Chinese Academy of Sciences(CLQ202516)the Fundamental Research Funds for the Central Universities of China(3282025047,3282024051,3282024009)。
文摘The advent of Grover’s algorithm presents a significant threat to classical block cipher security,spurring research into post-quantum secure cipher design.This study engineers quantum circuit implementations for three versions of the Ballet family block ciphers.The Ballet‑p/k includes a modular-addition operation uncommon in lightweight block ciphers.Quantum ripple-carry adder is implemented for both“32+32”and“64+64”scale to support this operation.Subsequently,qubits,quantum gates count,and quantum circuit depth of three versions of Ballet algorithm are systematically evaluated under quantum computing model,and key recovery attack circuits are constructed based on Grover’s algorithm against each version.The comprehensive analysis shows:Ballet-128/128 fails to NIST Level 1 security,while when the resource accounting is restricted to the Clifford gates and T gates set for the Ballet-128/256 and Ballet-256/256 quantum circuits,the design attains Level 3.
文摘Designing logic circuits using complementary metal-oxide-semiconductor(CMOS)technology at the nano scale has been faced with various challenges recently.Undesirable leakage currents,the short-effect channel,and high energy dissipation are some of the concerns.Quantum-dot cellular automata(QCA)represent an appropriate alternative for possible CMOS replacement in the future because it consumes an insignificant amount of energy compared to the standard CMOS.The key point of designing arithmetic circuits is based on the structure of a 1-bit full adder.A low-complexity full adder block is beneficial for developing various intricate structures.This paper represents scalable 1-bit QCA full adder structures based on cell interaction.Our proposed full adders encompass preference aspects of QCA design,such as a low number of cells used,low latency,and small area occupation.Also,the proposed structures have been expanded to larger circuits,including a 4-bit ripple carry adder(RCA),a 4-bit ripple borrow subtractor(RBS),an add/sub circuit,and a 2-bit array multiplier.All designs were simulated and verified using QCA Designer-E version 2.2.This tool can estimate the energy dissipation as well as evaluate the performance of the circuits.Simulation results showed that the proposed designs are efficient in complexity,area,latency,cost,and energy dissipation.
文摘Decimal arithmetic circuits are promising to provide a solution for accurate decimal arithmetic operations which are not possible with binary arithmetic circuits.They can be used in banking,commercial and financial transactions,scientific measurements,etc.This article presents the Very Large Scale Integration(VLSI)design of Binary Coded Decimal(BCD)-4221 area-optimized adder architecture using unconventional BCD-4221 representation.Unconventional BCD number representations such as BCD4221 also possess the additional advantage of more effectively representing the 10's complement representation which can be used to accelerate the decimal arithmetic operations.The design uses a binary Carry Lookahead Adder(CLA)along with some other logic blocks which are required to perform internal calculations with BCD-4221 numbers.The design is verified by using Xilinx Vivado 2016.1.Synthesis results have been obtained by Cadence Genus16.1 synthesis tool using 90 nm technology.The performance parameters such as area,power,delay,and area-delay Product(ADP)are compared with earlier reported circuits.Our proposed circuit shows significant area and ADP improvement over existing designs.
基金supported by the Grant number 600/1792 from the vice presidency of research and technology of Shahid Beheshti University,G.C
文摘This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFETbased ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characteristics of CNTFETs make them very suitable for designing high-performance multiple-Vth structures. The proposed structures reduce the number of the transistors considerably and have very high driving capability. The presented ternary Full Adders are simulated using Synopsys HSPICE with 32 nm CNTFET technology to evaluate their performance and to confirm their correct operation.
文摘New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.
文摘在现有全加器研究基础上,提出一种高性能全加器改进电路(improved full adder circuit,IFAC),通过改进全加器电路结构,优化电路元件工作数量,旨在提升加法器逻辑功能与运行状态。采用Candence软件搭载130 nm芯片锻造工艺,引入欧拉路径快速判寻法设计其电路版图,验证版图规则的合理性,并利用版图验证工具Dracula对电路进行仿真测试,结果表明本文所设计的全加器较常规全加器在处理复杂网络精确度、传输延迟时间、低功耗稳定运行及芯片面积方面有所提升。
基金financially supported by Shenzhen Fundamental Research Fund (No. JCYJ20210324120213037)Guangdong Special Support Project (No. 2019BT02X030)+8 种基金Shenzhen Peacock Group Plan (No. KQTD20180413181702403)Pearl River Recruitment Program of Talents (No. 2017GC010293)the National Natural Science Foundation of China (Nos. 11974298 and 61961136006)International Research Fellow of Japan Society for the Promotion of Science (JSPS), was supported by JSPS KAKENHI (No. JP20F20363)the support by the Grants-in-Aid for Scientific Research from JSPS KAKENHI (Nos. JP18H03676 and JP17K05490)the support by Core Research for Evolutionary Science and Technology, Japan Science and Technology Agency (Nos. JPMJCR20T2 and JPMJCR16F1)the support by the Grants-in-Aid for Scientific Research from JSPS KAKENHI (Nos. JP20F20363 and JP21H01364)the support by the National Natural Science Foundation of China (No. 12104327)the funding from the European Union’s Framework Program for Research and Innovation Horizon 2020 (No. 2014-2020) under the Marie Sk?odowska-Curie Grant Agreement No. 860060 (ITN MagnEFi)
文摘Skyrmion-based devices are promising candi-dates for non-volatile memory and low-delay time com-putation.Many skyrmion-based devices execute operation by controlling skyrmion trajectory,which can be impeded by the skyrmion Hall effect.Here,the design of skyrmion-based arithmetic devices built on synthetic antiferromag-netic(SyAF)structures is presented,where the structure can greatly suppress skyrmion Hall effect.In this study,the operations of skyrmion-based half adder,full adder,and XOR logic gate are executed by introducing geometric notches and tilted edges,which can annihilate or diverge skyrmion.Performance of these skyrmion-based devices is evaluated,where the delay time and energy-delay product of the single-bit full adder are 1.95 ns and 2.50×10^(-22)Js,which are only 12%and 79%those of the previously proposed skyrmion-based single-bit full adder.This improvement is significant in the construction of ripple-carry adder and ripple-carry adder-subtractor.Therefore,our skyrmion-based SyAF arithmetic device is a promising candidate to develop high-speed spintronic devices.
文摘The design of a three-input logic circuit using carbon nanotube field effect transistors(CNTFETs)is presented.Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital devices,which is why this design is so popular,and it also reduces chip area,both of which are examples of circuit overheads.The proposed module we have investigated is a triple-logic-based one,based on advanced technology CNTFETs and an emphasis on minimizing delay times at various values,as well as comparisons of the design working with various load capacitances.Comparing the proposed design with the existing design,the delay times was reduced from 66.32 to 16.41 ps,i.e.,a 75.26%reduction.However,the power dissipation was not optimized,and increased by 1.44%compared to the existing adder.The number of transistors was also reduced,and the product of power and delay(P∗D)achieved a value of 0.0498053 fJ.An improvement at 1 V was also achieved.A load capacitance(fF)was measured at different values,and the average delay measured for different values of capacitance had a maximum of 83.60 ps and a minimum of 22.54 ps,with a range of 61.06 ps.The power dissipations ranged from a minimum of 3.38μW to a maximum of 6.49μW.Based on these results,the use of this CNTFET half-adder design in multiple Boolean circuits will be a useful addition to circuit design.
文摘Compared with a sinusoidal operation, pulsed operation has more homogeneity and more efficiency in dielectric barrier discharge. In this paper, an improved pulse adder is designed and assembled to create repetitive high voltage rectangular pulses when resistive loads or capacitive loads exist. Beyond the normal pulse adder based on solid-state switches, additional metal- oxide-semiconductor field effect transistors are used in each stage for a faster falling edge. Further, the voltage difference between stages is eliminated by balancing windings. In this paper, we represent our theoretical derivation, software simulations and hardware experiments on magnetic self-balance. The experiments show that the voltage difference between stages is eliminated by balancing windings, which matches the result of simulations with almost identical circuits and parameters.
文摘The adders are the vital arithmetic operation for any arithmetic operations like multiplication,subtraction,and division.Binary number additions are performed by the digital circuit known as the adder.In VLSI(Very Large Scale Integration),the full adder is a basic component as it plays a major role in designing the integrated circuits applications.To minimize the power,various adder designs are implemented and each implemented designs undergo defined drawbacks.The designed adder requires high power when the driving capability is perfect and requires low power when the delay occurred is more.To overcome such issues and to obtain better performance,a novel parallel adder is proposed.The design of adder is initiated with 1 bit and has been extended up to 32 bits so as verify its scalability.This proposed novel parallel adder is attained from the carry look-ahead adder.The merits of this suggested adder are better speed,power consumption and delay,and the capability in driving.Thus designed adders are verified for different supply,delay,power,leakage and its performance is found to be superior to competitive Manchester Carry Chain Adder(MCCA),Carry Look Ahead Adder(CLAA),Carry Select Adder(CSLA),Carry Select Adder(CSA)and other adders.
文摘12001 Transformational Logic of Numbers of PurseEquivalence and its Error. Xiao Mingyao: 1(3). 1980pp 190--197Multiplier or counter --type adder can be usually used torealize the multiplication of two multidigit figures. Thispaper Introduces a Simple method, namely. the
文摘How cells accomplish cell size homeostasis is a fascinating topic, and several cell size regulation mechanisms were proposed: timer, sizer, and adder. Recently the adder model has received a great deal of attention. Adder property was also found in the DNA replication cycle. This paper aims to explain the adder phenomenon both in the division-centric picture and replication-centric picture at the molecular level. We established a self-replication model, and the system reached a steady state quickly based on evolution rules. We collected tens of thousands of cells in the same trajectory and calculated the Pearson correlation coefficient between biological variables to decide which regulatory mechanism was adopted by cells. Our simulation results confirmed the double-adder mechanism. Chromosome replication initiation and cell division control are independent and regulated by respective proteins.Cell size homeostasis originates from division control and has nothing to do with replication initiation control. At a slow growth rate, the deviation from adder toward sizer comes from a significant division protein degradation rate when division protein is auto-inhibited. Our results indicated the two necessary conditions in the double-adder mechanism: one is balanced biosynthesis, and the other is that there is a protein trigger threshold to inspire DNA replication initiation and cell division. Our results give insight to the regulatory mechanism of cell size and instructive to synthetic biology.
文摘Due to the demand of high computational speed for processing big data that requires complex data manipulations in a timely manner,the need for extending classical logic to construct new multi-valued optical models becomes a challenging and promising research area.This paper establishes a novel octal-valued logic design model with new optical gates construction based on the hypothesis of Light Color State Model to provide an efficient solution to the limitations of computational processing inherent in the electronics computing.We provide new mathematical definitions for both of the binary OR function and the PLUS operation in multi valued logic that is used as the basis of novel construction for the optical full adder model.Four case studies were used to assure the validity of the proposed adder.These cases proved that the proposed optical 8-valued logic models provide significantly more information to be packed within a single bit and therefore the abilities of data representation and processing is increased.
