A single-chip DVB-C quadrature amplitude modulation（QAM） demodulator is proposed,which integrates a 3.3V 10bit 40MSPS analog-to-digital converter and a forward error correction decoder. The demodulator chip can supp...A single-chip DVB-C quadrature amplitude modulation（QAM） demodulator is proposed,which integrates a 3.3V 10bit 40MSPS analog-to-digital converter and a forward error correction decoder. The demodulator chip can support 4-256 QAM with variable bit rate up to 80Mbps. It features a wide carrier offset acquisition range,optimal demodulation algorithm,and small circuit area. The chip is implemented in SMIC 0.25μm 1P5M mixed-signal CMOS technology with a die size of 3.5mm×3. 5mm. The maximum power consumption is 447mW.展开更多
The difference between circuit design stage and time requirements has broadened with the increasing complexity of the circuit.A big database is needed to undertake important analytical work like statistical method,hea...The difference between circuit design stage and time requirements has broadened with the increasing complexity of the circuit.A big database is needed to undertake important analytical work like statistical method,heat research,and IR-drop research that results in extended running times.This unit focuses on the assessment of test strength.Because of the enormous number of successful designs for currentmodels and the unnecessary time required for every test,maximum energy ratings with all tests cannot be achieved.Nevertheless,test safety is important for producing trustworthy findings to avoid loss of output and harm to the chip.Generally,effective power assessment is only possible in a limited sample of pre-selected experiments.Thus,a key objective is to find the experiments that might give the worst situations again for testing power.It offers a machine-based circuit power estimation(MLCPE)system for the selection of exams.Two distinct techniques of predicting are utilized.Firstly,to find testings with power dissipation,it forecasts the behavior of testing.Secondly,the changemovement and energy data are linked to the semiconductor design,identifying small problem areas.Several types of algorithms are utilized.In particular,the methods compared.The findings show great accuracy and efficiency in forecasting.That enables such methods suitable for selecting the worst scenario.展开更多
A novel divider based on dual-bit algorithm and its VLSI implementation are presented.Compared with the divider of MIPS microprocessor,it decreases the average executing cycles by 52.5% while its maximum delay is almo...A novel divider based on dual-bit algorithm and its VLSI implementation are presented.Compared with the divider of MIPS microprocessor,it decreases the average executing cycles by 52.5% while its maximum delay is almost the same and its transistor count increases by 60%.Furthermore,the simulation result indicates that the power consumption decreases to 11.3% with the same processing ability.展开更多
文摘A single-chip DVB-C quadrature amplitude modulation（QAM） demodulator is proposed,which integrates a 3.3V 10bit 40MSPS analog-to-digital converter and a forward error correction decoder. The demodulator chip can support 4-256 QAM with variable bit rate up to 80Mbps. It features a wide carrier offset acquisition range,optimal demodulation algorithm,and small circuit area. The chip is implemented in SMIC 0.25μm 1P5M mixed-signal CMOS technology with a die size of 3.5mm×3. 5mm. The maximum power consumption is 447mW.
基金supported by Dr S Karthik,SRM Institute of Science and TechnologySRM Institute of Science and Technology,Vadapalani Campus,Chennai,Tamilnadu,India。
文摘The difference between circuit design stage and time requirements has broadened with the increasing complexity of the circuit.A big database is needed to undertake important analytical work like statistical method,heat research,and IR-drop research that results in extended running times.This unit focuses on the assessment of test strength.Because of the enormous number of successful designs for currentmodels and the unnecessary time required for every test,maximum energy ratings with all tests cannot be achieved.Nevertheless,test safety is important for producing trustworthy findings to avoid loss of output and harm to the chip.Generally,effective power assessment is only possible in a limited sample of pre-selected experiments.Thus,a key objective is to find the experiments that might give the worst situations again for testing power.It offers a machine-based circuit power estimation(MLCPE)system for the selection of exams.Two distinct techniques of predicting are utilized.Firstly,to find testings with power dissipation,it forecasts the behavior of testing.Secondly,the changemovement and energy data are linked to the semiconductor design,identifying small problem areas.Several types of algorithms are utilized.In particular,the methods compared.The findings show great accuracy and efficiency in forecasting.That enables such methods suitable for selecting the worst scenario.
文摘A novel divider based on dual-bit algorithm and its VLSI implementation are presented.Compared with the divider of MIPS microprocessor,it decreases the average executing cycles by 52.5% while its maximum delay is almost the same and its transistor count increases by 60%.Furthermore,the simulation result indicates that the power consumption decreases to 11.3% with the same processing ability.
