The increasing trends in SoCs and SiPs technologies demand integration of large numbers of buses and metal tracks for interconnections. On-Chip SerDes Transceiver is a promising solution which can reduce the number of...The increasing trends in SoCs and SiPs technologies demand integration of large numbers of buses and metal tracks for interconnections. On-Chip SerDes Transceiver is a promising solution which can reduce the number of interconnects and offers remarkable benefits in context with power consumption, area congestion and crosstalk. This paper reports a design of a new Serializer and Deserializer architecture for basic functional operations of serialization and deserialization used in On-Chip SerDes Transceiver. This architecture employs a design technique which samples input on both edges of clock. The main advantage of this technique which is input is sampled with lower clock (half the original rate) and is distributed for the same functional throughput, which results in power savings in the clock distribution network. This proposed Serializer and Deserializer architecture is designed using UMC 180 nm CMOS technology and simulation is done using Cadence Spectre simulator with a supply voltage of 1.8 V. The present design is compared with the earlier published similar works and improvements are obtained in terms of power consumption and area as shown in Tables 1-3 respectively. This design also helps the designer for solving crosstalk issues.展开更多
车载通信是高速串行器与解串器(serializer and deserializer,SerDes)技术应用的一个重要领域。针对复杂车载环境中链路高频衰减导致的符号间干扰在高阶调制方式下更为严重的问题,引入深度学习方法,设计一种基于Transformer编码器结构...车载通信是高速串行器与解串器(serializer and deserializer,SerDes)技术应用的一个重要领域。针对复杂车载环境中链路高频衰减导致的符号间干扰在高阶调制方式下更为严重的问题,引入深度学习方法,设计一种基于Transformer编码器结构的低复杂度信道均衡方案,以提高接收信号质量。该方案将输入序列转换为抽象的表示向量,然后利用编码器层提取表示向量的特征信息,最后全连接层根据特征信息对信号进行分类,从而实现高速SerDes信道均衡。实验结果表明:与传统自适应算法和全连接神经网络模型相比,所提方案能够有效降低高频衰减导致的信号失真,在计算复杂度降低19%和24%的情况下接收信噪比增益分别为1.8 dB和0.9 dB。通过在高速SerDes系统中应用所提信道均衡方案,可以提高信号传输质量以及增强系统的鲁棒性。展开更多
The current massive use of digital communications demands a secure link by using an embedded system（ES） with data encryption at the protocol level. The serial peripheral interface（SPI） protocol is commonly used by...The current massive use of digital communications demands a secure link by using an embedded system（ES） with data encryption at the protocol level. The serial peripheral interface（SPI） protocol is commonly used by manufacturers of ESs and integrated circuits for applications in areas such as wired and wireless communications. We present the design and experimental implementation of a chaotic encryption and decryption algorithm applied to the SPI communication protocol. The design of the chaotic encryption algorithm along with its counterpart in the decryption is based on the chaotic Hénon map and two methods for blur and permute（in combination with DNA sequences）. The SPI protocol is configured in 16 bits to synchronize a transmitter and a receiver considering a symmetric key. Results are experimentally proved using two low-cost dsPIC microcontrollers as ESs. The SPI digital-to-analog converter is used to process, acquire, and reconstruct confidential messages based on its properties for digital signal processing. Finally, security of the cryptogram is proved by a statistical test. The digital processing capacity of the algorithm is validated by dsPIC microcontrollers.展开更多
Previous efforts to boost the performance of brain-computer interfaces (BCIs) have predominantly focused on optimizing algorithms for decoding brain signals. However, the untapped potential of leveraging brain plastic...Previous efforts to boost the performance of brain-computer interfaces (BCIs) have predominantly focused on optimizing algorithms for decoding brain signals. However, the untapped potential of leveraging brain plasticity for optimization remains underexplored. In this study, we enhanced the temporal resolution of the human brain in discriminating visual stimuli by eliminating the attentional blink (AB) through color-salient cognitive training, and we confirmed that the mechanism was an attention-based improvement. Using the rapid serial visual presentation (RSVP)-based BCI, we evaluated the behavioral and electroencephalogram (EEG) decoding performance of subjects before and after cognitive training in high target percentage (with AB) and low target percentage (without AB) surveillance tasks, respectively. The results consistently demonstrated significant improvements in the trained subjects. Further analysis indicated that this improvement was attributed to the cognitively trained brain producing more discriminative EEG. Our work highlights the feasibility of cognitive training as a means of brain enhancement to boost BCI performance.展开更多
文摘The increasing trends in SoCs and SiPs technologies demand integration of large numbers of buses and metal tracks for interconnections. On-Chip SerDes Transceiver is a promising solution which can reduce the number of interconnects and offers remarkable benefits in context with power consumption, area congestion and crosstalk. This paper reports a design of a new Serializer and Deserializer architecture for basic functional operations of serialization and deserialization used in On-Chip SerDes Transceiver. This architecture employs a design technique which samples input on both edges of clock. The main advantage of this technique which is input is sampled with lower clock (half the original rate) and is distributed for the same functional throughput, which results in power savings in the clock distribution network. This proposed Serializer and Deserializer architecture is designed using UMC 180 nm CMOS technology and simulation is done using Cadence Spectre simulator with a supply voltage of 1.8 V. The present design is compared with the earlier published similar works and improvements are obtained in terms of power consumption and area as shown in Tables 1-3 respectively. This design also helps the designer for solving crosstalk issues.
基金Acknowledgements： This work was partially supported by Natural Science Foundation of Liaoning Province, China （No. 20042042）, Specialized Research Fund for the Doctoral Program of Higher Education of China （No. 20030145017）.
文摘车载通信是高速串行器与解串器(serializer and deserializer,SerDes)技术应用的一个重要领域。针对复杂车载环境中链路高频衰减导致的符号间干扰在高阶调制方式下更为严重的问题,引入深度学习方法,设计一种基于Transformer编码器结构的低复杂度信道均衡方案,以提高接收信号质量。该方案将输入序列转换为抽象的表示向量,然后利用编码器层提取表示向量的特征信息,最后全连接层根据特征信息对信号进行分类,从而实现高速SerDes信道均衡。实验结果表明:与传统自适应算法和全连接神经网络模型相比,所提方案能够有效降低高频衰减导致的信号失真,在计算复杂度降低19%和24%的情况下接收信噪比增益分别为1.8 dB和0.9 dB。通过在高速SerDes系统中应用所提信道均衡方案,可以提高信号传输质量以及增强系统的鲁棒性。
基金Project supported by the CONACYT,México(No.166654)
文摘The current massive use of digital communications demands a secure link by using an embedded system（ES） with data encryption at the protocol level. The serial peripheral interface（SPI） protocol is commonly used by manufacturers of ESs and integrated circuits for applications in areas such as wired and wireless communications. We present the design and experimental implementation of a chaotic encryption and decryption algorithm applied to the SPI communication protocol. The design of the chaotic encryption algorithm along with its counterpart in the decryption is based on the chaotic Hénon map and two methods for blur and permute（in combination with DNA sequences）. The SPI protocol is configured in 16 bits to synchronize a transmitter and a receiver considering a symmetric key. Results are experimentally proved using two low-cost dsPIC microcontrollers as ESs. The SPI digital-to-analog converter is used to process, acquire, and reconstruct confidential messages based on its properties for digital signal processing. Finally, security of the cryptogram is proved by a statistical test. The digital processing capacity of the algorithm is validated by dsPIC microcontrollers.
基金supported by the National Natural Science Foundation of China (U19B2030, 61976167, 62301405, 62101416)the Natural Science Basic Research Program of Shaanxi, China (2022JQ-708)Fundamental Research Funds for the Central Universities, China.
文摘Previous efforts to boost the performance of brain-computer interfaces (BCIs) have predominantly focused on optimizing algorithms for decoding brain signals. However, the untapped potential of leveraging brain plasticity for optimization remains underexplored. In this study, we enhanced the temporal resolution of the human brain in discriminating visual stimuli by eliminating the attentional blink (AB) through color-salient cognitive training, and we confirmed that the mechanism was an attention-based improvement. Using the rapid serial visual presentation (RSVP)-based BCI, we evaluated the behavioral and electroencephalogram (EEG) decoding performance of subjects before and after cognitive training in high target percentage (with AB) and low target percentage (without AB) surveillance tasks, respectively. The results consistently demonstrated significant improvements in the trained subjects. Further analysis indicated that this improvement was attributed to the cognitively trained brain producing more discriminative EEG. Our work highlights the feasibility of cognitive training as a means of brain enhancement to boost BCI performance.
