An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an intern...An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy（TMR）,which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.展开更多
Static random-access memory(SRAM)-based eld programmable gate arrays(FPGAs)are sensitive to radiationinduced single event upsets(SEUs)^([1]).Single-bit upsets(SBUs),as a well-known effect in FPGAs,occur when the energ...Static random-access memory(SRAM)-based eld programmable gate arrays(FPGAs)are sensitive to radiationinduced single event upsets(SEUs)^([1]).Single-bit upsets(SBUs),as a well-known effect in FPGAs,occur when the energy deposited by a single particle(such as heavy ion)exceeds the critical charge in single memory cell.However,in modern advanced process technologies,owing to the smaller area and decreased critical charge of transistors.展开更多
SRAM-based FPGAs are very susceptible to radiation-induced Single-Event Upsets （SEUs） in space applications. The failure mechanism in FPGA＇s configuration memory differs from those in traditional memory device. As ...SRAM-based FPGAs are very susceptible to radiation-induced Single-Event Upsets （SEUs） in space applications. The failure mechanism in FPGA＇s configuration memory differs from those in traditional memory device. As a result, there is a growing demand for methodologies which could quantitatively evaluate the impact of this effect. Fault injection appears to meet such requirement. In this paper, we propose a new methodology to analyze the soft errors in SRAM-based FPGAs. This method is based on in depth understanding of the device architecture and failure mechanisms induced by configuration upsets. The developed programs read in the placed and routed netlist, search for critical logic nodes and paths that may destroy the circuit topological structure, and then query a database storing the decoded relationship of the configurable resources and corresponding control bit to get the sensitive bits. Accelerator irradiation test and fault injection experiments were carried out to validate this approach.展开更多
基金Supported by the National High Technology and Development Program of China(2013AA1548)
文摘An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy（TMR）,which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.
基金National Natural Science Foundation of China(12035019,11690041)。
文摘Static random-access memory(SRAM)-based eld programmable gate arrays(FPGAs)are sensitive to radiationinduced single event upsets(SEUs)^([1]).Single-bit upsets(SBUs),as a well-known effect in FPGAs,occur when the energy deposited by a single particle(such as heavy ion)exceeds the critical charge in single memory cell.However,in modern advanced process technologies,owing to the smaller area and decreased critical charge of transistors.
基金Project supported by the National Natural Science Foundation of China(No.10875096).
文摘SRAM-based FPGAs are very susceptible to radiation-induced Single-Event Upsets （SEUs） in space applications. The failure mechanism in FPGA＇s configuration memory differs from those in traditional memory device. As a result, there is a growing demand for methodologies which could quantitatively evaluate the impact of this effect. Fault injection appears to meet such requirement. In this paper, we propose a new methodology to analyze the soft errors in SRAM-based FPGAs. This method is based on in depth understanding of the device architecture and failure mechanisms induced by configuration upsets. The developed programs read in the placed and routed netlist, search for critical logic nodes and paths that may destroy the circuit topological structure, and then query a database storing the decoded relationship of the configurable resources and corresponding control bit to get the sensitive bits. Accelerator irradiation test and fault injection experiments were carried out to validate this approach.
