Silicon Carbide (SiC) machining by traditional methods with regards to its high hardness is not possible. Electro Discharge Machining, among non-traditional machining methods, is used for machining of SiC. The present...Silicon Carbide (SiC) machining by traditional methods with regards to its high hardness is not possible. Electro Discharge Machining, among non-traditional machining methods, is used for machining of SiC. The present work is aimed to optimize the surface roughness and material removal rate of electro discharge machining of SiC parameters simultaneously. As the output parameters are conflicting in nature, so there is no single combination of machining parameters, which provides the best machining performance. Artificial neural network (ANN) with back propagation algorithm is used to model the process. A multi-objective optimization method, non-dominating sorting genetic algorithm-II is used to optimize the process. Affects of three important input parameters of process viz., discharge current, pulse on time (Ton), pulse off time (Toff) on electric discharge machining of SiC are considered. Experiments have been conducted over a wide range of considered input parameters for training and verification of the model. Testing results demonstrate that the model is suitable for predicting the response parameters. A pareto-optimal set has been predicted in this work.展开更多
完成了一种基于ROM结构的直接数字频率合成器(Direct Digital Synthesizer,DDS)的ASIC设计。其中累加器采用进位链和流水线相结合的方式,提高了工作频率的同时降低了资源占用率;ROM模块应用以正弦函数1/4波形对称性为基础,并结合Hutchi...完成了一种基于ROM结构的直接数字频率合成器(Direct Digital Synthesizer,DDS)的ASIC设计。其中累加器采用进位链和流水线相结合的方式,提高了工作频率的同时降低了资源占用率;ROM模块应用以正弦函数1/4波形对称性为基础,并结合Hutchison相交分离法的改进压缩算法,压缩率达到49倍,降低了芯片的功耗和面积。基于SMIC 0.18μm CMOS工艺库完成了后端物理设计和后仿真。该DDS功耗低,面积小,频率分辨率高,可作为高质量的信号源应用于4G移动通信中。展开更多
提出了一种简洁、新颖的SiC MOSFET器件导通电阻模型,该模型采用遗传算法对其不同温度下的导通电阻进行准确描述。相比于传统的导通电阻建模方案,采用进化算法可以准确地得到MOSFET导通电阻与结温之间的关系。并探究了不同种群规模、交...提出了一种简洁、新颖的SiC MOSFET器件导通电阻模型,该模型采用遗传算法对其不同温度下的导通电阻进行准确描述。相比于传统的导通电阻建模方案,采用进化算法可以准确地得到MOSFET导通电阻与结温之间的关系。并探究了不同种群规模、交叉率和变异率对算法的影响。为了验证模型的准确性,采用一款自主封装的1200 V/90 A SiC MOSFET模块去验证模型的静态特性,并与传统导通电阻建模方案进行对比,其最大误差为4.1%。展开更多
针对以感知波形为基础的信号在通感一体化(Integrated sensing and communication,ISAC)系统中面临通信速率低、易被截获等问题,本文设计了一种基于正交相移键控(Quadrature phase shift keying,QPSK)与线性调频信号(Linear frequency m...针对以感知波形为基础的信号在通感一体化(Integrated sensing and communication,ISAC)系统中面临通信速率低、易被截获等问题,本文设计了一种基于正交相移键控(Quadrature phase shift keying,QPSK)与线性调频信号(Linear frequency modulation,LFM)的多路跳频传输架构。该架构利用多个LFM信号同时在重叠的频谱区间传输以提高符号速率,并通过LFM子载波的跳频特性实现加密通信。此外,通过结合动态前导码与数据的时分复用机制,该方案有效地提升了多路LFM信号的路径索引和参数估计精度。针对符号解调,本文提出两种基于非相干离散啁啾傅里叶变换(Noncoherent discrete chirp Fourier transform,NC⁃DCFT)的多峰值检测算法。仿真结果表明,在相同符号速率约束下,本文所提出的多路并行架构在误码率方面优于传统单路方案,当信噪比为0 dB时,4路并行架构的误码率相较于单路方案降低了一个数量级。同时,动态前导码方案满足不同场景下的路径索引识别需求,在信噪比为0 dB时,归一化均方差均低于10-2。此外,面向功率均衡、功率差异显著及载波参数保护间隔较小3种复杂场景设计的符号检测算法,在其适配场景下均可实现误码率低于10-2。最后,跳频机制显著增强了系统的抗截获能力,即使50%参数泄露,第3方对信号的恢复概率(Probability of accurate recovery,PAR)仍被压制在7%以下,验证了该方案的鲁棒性与应用价值。展开更多
文摘Silicon Carbide (SiC) machining by traditional methods with regards to its high hardness is not possible. Electro Discharge Machining, among non-traditional machining methods, is used for machining of SiC. The present work is aimed to optimize the surface roughness and material removal rate of electro discharge machining of SiC parameters simultaneously. As the output parameters are conflicting in nature, so there is no single combination of machining parameters, which provides the best machining performance. Artificial neural network (ANN) with back propagation algorithm is used to model the process. A multi-objective optimization method, non-dominating sorting genetic algorithm-II is used to optimize the process. Affects of three important input parameters of process viz., discharge current, pulse on time (Ton), pulse off time (Toff) on electric discharge machining of SiC are considered. Experiments have been conducted over a wide range of considered input parameters for training and verification of the model. Testing results demonstrate that the model is suitable for predicting the response parameters. A pareto-optimal set has been predicted in this work.
文摘完成了一种基于ROM结构的直接数字频率合成器(Direct Digital Synthesizer,DDS)的ASIC设计。其中累加器采用进位链和流水线相结合的方式,提高了工作频率的同时降低了资源占用率;ROM模块应用以正弦函数1/4波形对称性为基础,并结合Hutchison相交分离法的改进压缩算法,压缩率达到49倍,降低了芯片的功耗和面积。基于SMIC 0.18μm CMOS工艺库完成了后端物理设计和后仿真。该DDS功耗低,面积小,频率分辨率高,可作为高质量的信号源应用于4G移动通信中。
文摘提出了一种简洁、新颖的SiC MOSFET器件导通电阻模型,该模型采用遗传算法对其不同温度下的导通电阻进行准确描述。相比于传统的导通电阻建模方案,采用进化算法可以准确地得到MOSFET导通电阻与结温之间的关系。并探究了不同种群规模、交叉率和变异率对算法的影响。为了验证模型的准确性,采用一款自主封装的1200 V/90 A SiC MOSFET模块去验证模型的静态特性,并与传统导通电阻建模方案进行对比,其最大误差为4.1%。
文摘针对以感知波形为基础的信号在通感一体化(Integrated sensing and communication,ISAC)系统中面临通信速率低、易被截获等问题,本文设计了一种基于正交相移键控(Quadrature phase shift keying,QPSK)与线性调频信号(Linear frequency modulation,LFM)的多路跳频传输架构。该架构利用多个LFM信号同时在重叠的频谱区间传输以提高符号速率,并通过LFM子载波的跳频特性实现加密通信。此外,通过结合动态前导码与数据的时分复用机制,该方案有效地提升了多路LFM信号的路径索引和参数估计精度。针对符号解调,本文提出两种基于非相干离散啁啾傅里叶变换(Noncoherent discrete chirp Fourier transform,NC⁃DCFT)的多峰值检测算法。仿真结果表明,在相同符号速率约束下,本文所提出的多路并行架构在误码率方面优于传统单路方案,当信噪比为0 dB时,4路并行架构的误码率相较于单路方案降低了一个数量级。同时,动态前导码方案满足不同场景下的路径索引识别需求,在信噪比为0 dB时,归一化均方差均低于10-2。此外,面向功率均衡、功率差异显著及载波参数保护间隔较小3种复杂场景设计的符号检测算法,在其适配场景下均可实现误码率低于10-2。最后,跳频机制显著增强了系统的抗截获能力,即使50%参数泄露,第3方对信号的恢复概率(Probability of accurate recovery,PAR)仍被压制在7%以下,验证了该方案的鲁棒性与应用价值。
