In this research, the denoising of speckled SAR image has been done with fuzzy filters (ATMED, TMED, ATMAV & TMAV). SAR image or Synthetic Aperture Radar image consists of the informatics of ISW (Internal solitary...In this research, the denoising of speckled SAR image has been done with fuzzy filters (ATMED, TMED, ATMAV & TMAV). SAR image or Synthetic Aperture Radar image consists of the informatics of ISW (Internal solitary waves). A new technique has been proposed which preserved the edge pixels by fuzzy edge detection method and then altered with the filtered image-pixels by fuzzy filtration for getting the denoised image. The comparative result shows that the proposed filter performs better than the other filtered results in terms of PSNR (41.61 dB), MAE (1.47), MSE (4.54) for TMAVxAPE & SSIM (81%) for ATMEDwAPE. The proposed method in this research shows better SSI (Spackle Suppression Index) value. Therefore the experimental result illustrates that the suggested fuzzy filter is much more capable of simultaneously protecting edges and suppressing speckle noise. This research will be beneficial to remove spackle noise from SAR images and can be used for remote sensing and mapping of surface area of earth.展开更多
High precision and large dynamic range measurement ave required in the readout systems for the Water Cherenkov Detector Array （WCDA） in the Large High Altitude Air Shower Observatory （LHAASO）. This paper presents ...High precision and large dynamic range measurement ave required in the readout systems for the Water Cherenkov Detector Array （WCDA） in the Large High Altitude Air Shower Observatory （LHAASO）. This paper presents a prototype of a 12-bit 40 MSPS Analog-to-Digital Converter （ADC） Application Specific Integrated Circuit （ASIC） designed for the readout of the LHAASO WCDA. Combining this ADC and the front-end ASIC finished in our previous work, high precision charge measurement can be achieved based on the digital peak detection method. This ADC is implemented based on a power-efficient Successive Approximation Register （SAR） architecture, which incorporates key parts such as a Capacitive Digital-to-Analog Converter （CDAC）, dynamic compavator and asyn- chronous SAR control logic. The simulation results indicate that the Effective Number Of Bits （ENOB） with a sampling rate of 40 MSPS is better than 10 bits in an input frequency range below 20 MHz, while its core power consumption is 6.6 mW per channel. The above results are good enough for the readout requirements of the WCDA.展开更多
This paper presents a 10-bit 50-MS/s subrange successive-approximation register （SAR） analog-to- digital converter （ADC） composed of a 4-bit SAR coarse ADC and a 6-bit SAR fine ADC. In the coarse ADC, multi- compa...This paper presents a 10-bit 50-MS/s subrange successive-approximation register （SAR） analog-to- digital converter （ADC） composed of a 4-bit SAR coarse ADC and a 6-bit SAR fine ADC. In the coarse ADC, multi- comparator SAR architecture is used to reduce the digital logic propagation delay, and a traditional asynchronous SAR ADC with monotonic switching method is used as the fine ADC. With that combination, power dissipation also can be much reduced. Meanwhile, a modified SAR control logic is adopted in the fine ADC to speed up the conversion and other techniques, such as splitting capacitors array, are borrowed to reduce the power consumption. Fabricated with 1PSM 130-nm CMOS technology, the proposed SAR ADC achieves 51.6-dB signal to noise and distortion ratio （SNDR） and consumes 186μW at 50 MS/s with a 1-V supply, resulting in a figure of merit （FOM） of 12 fJ/conversion-step. The core area is only 0.045 mm2.展开更多
This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register （SAR） analog-to-digital converter （ADC） in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed, a new wi...This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register （SAR） analog-to-digital converter （ADC） in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed, a new window-opening logic based on the asynchronous SAR algorithm is proposed to minimize the logic delay, and a partial set-and-down DAC with binary redundancy bits is presented to reduce the dynamic comparator offset and accelerate the DAC settling. Besides, a new bootstrapped switch with a pre-charge phase is adopted in the track and hold circuits to increase speed and reduce area. The presented ADC achieves 52.9 dB signal-to-noise distortion ratio and 65 dB spurious-free dynamic range measured with a 30 MHz input signal at 160 MHz clock. The power consumption is 9.5 mW and a core die area of 250 ×200 μm^2 is occupied.展开更多
This paper presents a 10 bit successive approximation register （SAR） analog-to-digital converter （ADC） in 0.18 μm 1P6M CMOS technology with a 1.8 V supply voltage. To improve the conversion speed, a partial split...This paper presents a 10 bit successive approximation register （SAR） analog-to-digital converter （ADC） in 0.18 μm 1P6M CMOS technology with a 1.8 V supply voltage. To improve the conversion speed, a partial split capacitor switching scheme is proposed. By reducing the time constant of the bit cycles, the proposed technique shortens the settling time of a capacitive digital-to-analog converter （DAC）. In addition, a new SAR control logic is proposed to reduce loop delay to further enhance the conversion speed. At 1.8 V supply voltage and 50 MS/s the SAR ADC achieves a signal-to-noise and distortion ratio （SNDR） of 57.5 dB and spurious-free dynamic range （SFDR） of 69.3 dB. The power consumption is 2.26 mW and the core die area is 0.096 mm2.展开更多
This paper presents a power-efficient 100-MS/s,10-bit asynchronous successive approximation register（SAR） ADC.It includes an on-chip reference buffer and the total power dissipation is 6.8 mW.To achieve high perform...This paper presents a power-efficient 100-MS/s,10-bit asynchronous successive approximation register（SAR） ADC.It includes an on-chip reference buffer and the total power dissipation is 6.8 mW.To achieve high performance with high power-efficiency in the proposed ADC,bootstrapped switch,redundancy,set-and-down switching approach,dynamic comparator and dynamic logic techniques are employed.The prototype was fabricated using 65 nm standard CMOS technology.At a 1.2-V supply and 100 MS/s,the ADC achieves an SNDR of 56.2 dB and a SFDR of 65.1 dB.The ADC core consumes only 3.1 mW,resulting in a figure of merit（FOM） of 30.27 fJ/conversionstep and occupies an active area of only 0.009 mm^2.展开更多
This paper presents a low power 9-bit 80 MS/s SAR ADC with comparator-sharing technique in 130 nm CMOS process. Compared to the conventional SAR ADC, the sampling phase is removed to reach the full efficiency of the c...This paper presents a low power 9-bit 80 MS/s SAR ADC with comparator-sharing technique in 130 nm CMOS process. Compared to the conventional SAR ADC, the sampling phase is removed to reach the full efficiency of the comparator. Thus the conversion rate increases by about 20% and its sampling time is relaxed. The design does not use any static components to achieve a widely scalable conversion rate with a constant FOM. The floorplan of the capacitor network is custom-designed to suppress the gain mismatch between the two DACs. The ＇set-and- down＇ switching procedure and a novel binary-search error compensation scheme are utilized to further speed up the SA bit-cycling operation. A very fast logic controller is proposed with a delay time of only 90 ps. At 1.2 V supply and 80 MS/s the ADC achieves an SNDR of 51.4 dB and consumes 1.86 mW, resulting in an FOM of 76.6 fJ/conversion-step. The ADC core occupies an active area of only 0.089 mm2.展开更多
文摘In this research, the denoising of speckled SAR image has been done with fuzzy filters (ATMED, TMED, ATMAV & TMAV). SAR image or Synthetic Aperture Radar image consists of the informatics of ISW (Internal solitary waves). A new technique has been proposed which preserved the edge pixels by fuzzy edge detection method and then altered with the filtered image-pixels by fuzzy filtration for getting the denoised image. The comparative result shows that the proposed filter performs better than the other filtered results in terms of PSNR (41.61 dB), MAE (1.47), MSE (4.54) for TMAVxAPE & SSIM (81%) for ATMEDwAPE. The proposed method in this research shows better SSI (Spackle Suppression Index) value. Therefore the experimental result illustrates that the suggested fuzzy filter is much more capable of simultaneously protecting edges and suppressing speckle noise. This research will be beneficial to remove spackle noise from SAR images and can be used for remote sensing and mapping of surface area of earth.
基金Supported by Knowledge Innovation Program of the Chinese Academy of Sciences(KJCX2-YW-N27)CAS Center for Excellence in Particle Physics(CCEPP)
文摘High precision and large dynamic range measurement ave required in the readout systems for the Water Cherenkov Detector Array （WCDA） in the Large High Altitude Air Shower Observatory （LHAASO）. This paper presents a prototype of a 12-bit 40 MSPS Analog-to-Digital Converter （ADC） Application Specific Integrated Circuit （ASIC） designed for the readout of the LHAASO WCDA. Combining this ADC and the front-end ASIC finished in our previous work, high precision charge measurement can be achieved based on the digital peak detection method. This ADC is implemented based on a power-efficient Successive Approximation Register （SAR） architecture, which incorporates key parts such as a Capacitive Digital-to-Analog Converter （CDAC）, dynamic compavator and asyn- chronous SAR control logic. The simulation results indicate that the Effective Number Of Bits （ENOB） with a sampling rate of 40 MSPS is better than 10 bits in an input frequency range below 20 MHz, while its core power consumption is 6.6 mW per channel. The above results are good enough for the readout requirements of the WCDA.
基金Project supported by the National Natural Science Foundation of China(Nos.61204033,61331015)the Fundamental Research Funds for the Central Universities(No.WK2100230015)the Funds of Science and Technology on Analog Integrated Circuit Laboratory(No.9140C090111150C09041)
文摘This paper presents a 10-bit 50-MS/s subrange successive-approximation register （SAR） analog-to- digital converter （ADC） composed of a 4-bit SAR coarse ADC and a 6-bit SAR fine ADC. In the coarse ADC, multi- comparator SAR architecture is used to reduce the digital logic propagation delay, and a traditional asynchronous SAR ADC with monotonic switching method is used as the fine ADC. With that combination, power dissipation also can be much reduced. Meanwhile, a modified SAR control logic is adopted in the fine ADC to speed up the conversion and other techniques, such as splitting capacitors array, are borrowed to reduce the power consumption. Fabricated with 1PSM 130-nm CMOS technology, the proposed SAR ADC achieves 51.6-dB signal to noise and distortion ratio （SNDR） and consumes 186μW at 50 MS/s with a 1-V supply, resulting in a figure of merit （FOM） of 12 fJ/conversion-step. The core area is only 0.045 mm2.
文摘This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register （SAR） analog-to-digital converter （ADC） in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed, a new window-opening logic based on the asynchronous SAR algorithm is proposed to minimize the logic delay, and a partial set-and-down DAC with binary redundancy bits is presented to reduce the dynamic comparator offset and accelerate the DAC settling. Besides, a new bootstrapped switch with a pre-charge phase is adopted in the track and hold circuits to increase speed and reduce area. The presented ADC achieves 52.9 dB signal-to-noise distortion ratio and 65 dB spurious-free dynamic range measured with a 30 MHz input signal at 160 MHz clock. The power consumption is 9.5 mW and a core die area of 250 ×200 μm^2 is occupied.
基金supported by the National Natural Science Foundation of China(No.61401097)
文摘This paper presents a 10 bit successive approximation register （SAR） analog-to-digital converter （ADC） in 0.18 μm 1P6M CMOS technology with a 1.8 V supply voltage. To improve the conversion speed, a partial split capacitor switching scheme is proposed. By reducing the time constant of the bit cycles, the proposed technique shortens the settling time of a capacitive digital-to-analog converter （DAC）. In addition, a new SAR control logic is proposed to reduce loop delay to further enhance the conversion speed. At 1.8 V supply voltage and 50 MS/s the SAR ADC achieves a signal-to-noise and distortion ratio （SNDR） of 57.5 dB and spurious-free dynamic range （SFDR） of 69.3 dB. The power consumption is 2.26 mW and the core die area is 0.096 mm2.
文摘This paper presents a power-efficient 100-MS/s,10-bit asynchronous successive approximation register（SAR） ADC.It includes an on-chip reference buffer and the total power dissipation is 6.8 mW.To achieve high performance with high power-efficiency in the proposed ADC,bootstrapped switch,redundancy,set-and-down switching approach,dynamic comparator and dynamic logic techniques are employed.The prototype was fabricated using 65 nm standard CMOS technology.At a 1.2-V supply and 100 MS/s,the ADC achieves an SNDR of 56.2 dB and a SFDR of 65.1 dB.The ADC core consumes only 3.1 mW,resulting in a figure of merit（FOM） of 30.27 fJ/conversionstep and occupies an active area of only 0.009 mm^2.
基金Project supported by the Natural Science Foundation for Key Program of Jiangsu Higher Education Institutions(No.09KJA510001)
文摘This paper presents a low power 9-bit 80 MS/s SAR ADC with comparator-sharing technique in 130 nm CMOS process. Compared to the conventional SAR ADC, the sampling phase is removed to reach the full efficiency of the comparator. Thus the conversion rate increases by about 20% and its sampling time is relaxed. The design does not use any static components to achieve a widely scalable conversion rate with a constant FOM. The floorplan of the capacitor network is custom-designed to suppress the gain mismatch between the two DACs. The ＇set-and- down＇ switching procedure and a novel binary-search error compensation scheme are utilized to further speed up the SA bit-cycling operation. A very fast logic controller is proposed with a delay time of only 90 ps. At 1.2 V supply and 80 MS/s the ADC achieves an SNDR of 51.4 dB and consumes 1.86 mW, resulting in an FOM of 76.6 fJ/conversion-step. The ADC core occupies an active area of only 0.089 mm2.
