New technologies such as quantum-dot cellular automata(QCA) have been showing some remarkable characteristics that standard complementary-metal-oxide semiconductor(CMOS) in deep sub-micron cannot afford. Modeling syst...New technologies such as quantum-dot cellular automata(QCA) have been showing some remarkable characteristics that standard complementary-metal-oxide semiconductor(CMOS) in deep sub-micron cannot afford. Modeling systems and designing multiple-valued logic gates with QCA have advantages that facilitate the design of complicated logic circuits. In this paper, we propose a novel creative concept for quaternary QCA(QQCA). The concept has been set in QCASim, the new simulator developed by our team exclusively for QCAs’ quaternary mode. Proposed basic quaternary logic gates such as MIN, MAX, and different types of inverters(SQI, PQI, NQI, and IQI) have been designed and verified by QCASim. This study will exemplify how fast and accurately QCASim works by its handy set of CAD tools. A 1×4 decoder is presented using our proposed main gates.Preference points such as the minimum delay, area, and complexity have been achieved in this work. QQCA main logic gates are compared with quaternary gates based on carbon nanotube field-effect transistor(CNFET). The results show that the proposed design is more efficient in terms of latency and energy consumption.展开更多
CMOS binary logic is limited by short channel effects, power density, and interconnection restrictions. The effective solution is non-silicon multiple-valued logic （MVL） computing. This study presents two high-perfo...CMOS binary logic is limited by short channel effects, power density, and interconnection restrictions. The effective solution is non-silicon multiple-valued logic （MVL） computing. This study presents two high-performance quaternary full adder cells based on carbon nanotube field effect transistors （CNTFETs）. The proposed designs use the unique properties of CNTFETs such as achieving a desired threshold voltage by adjusting the carbon nanotube diameters and having the same mobility as p-type and n-type devices. The proposed circuits were simulated under various test conditions using the Synopsys HSPICE simulator with the 32 nm Stanford comprehensive CNTFET model. The proposed designs have on average 32% lower delay, 68% average power, 83% energy consumption, and 77% static power compared to current state-of-the-art quaternary full adders. Simulation results indicated that the proposed designs are robust against process, voltage, and temperature variations, and are noise tolerant.展开更多
文摘New technologies such as quantum-dot cellular automata(QCA) have been showing some remarkable characteristics that standard complementary-metal-oxide semiconductor(CMOS) in deep sub-micron cannot afford. Modeling systems and designing multiple-valued logic gates with QCA have advantages that facilitate the design of complicated logic circuits. In this paper, we propose a novel creative concept for quaternary QCA(QQCA). The concept has been set in QCASim, the new simulator developed by our team exclusively for QCAs’ quaternary mode. Proposed basic quaternary logic gates such as MIN, MAX, and different types of inverters(SQI, PQI, NQI, and IQI) have been designed and verified by QCASim. This study will exemplify how fast and accurately QCASim works by its handy set of CAD tools. A 1×4 decoder is presented using our proposed main gates.Preference points such as the minimum delay, area, and complexity have been achieved in this work. QQCA main logic gates are compared with quaternary gates based on carbon nanotube field-effect transistor(CNFET). The results show that the proposed design is more efficient in terms of latency and energy consumption.
文摘CMOS binary logic is limited by short channel effects, power density, and interconnection restrictions. The effective solution is non-silicon multiple-valued logic （MVL） computing. This study presents two high-performance quaternary full adder cells based on carbon nanotube field effect transistors （CNTFETs）. The proposed designs use the unique properties of CNTFETs such as achieving a desired threshold voltage by adjusting the carbon nanotube diameters and having the same mobility as p-type and n-type devices. The proposed circuits were simulated under various test conditions using the Synopsys HSPICE simulator with the 32 nm Stanford comprehensive CNTFET model. The proposed designs have on average 32% lower delay, 68% average power, 83% energy consumption, and 77% static power compared to current state-of-the-art quaternary full adders. Simulation results indicated that the proposed designs are robust against process, voltage, and temperature variations, and are noise tolerant.
