The paper analyzes and compares the phase margins of four active disturbance rejection control(ADRC)designs,which are based on different common-used extended state observers(ESOs)of various orders,for second-order sys...The paper analyzes and compares the phase margins of four active disturbance rejection control(ADRC)designs,which are based on different common-used extended state observers(ESOs)of various orders,for second-order systems.The quantitative results indicate that,besides good dynamic response,ADRC can guarantee enough phase margin.It is also proved that by decreasing the order of ESO,the phase margin can be increased.Furthermore,it is demonstrated that the phase margins of the ADRC-based systems can be almost uninfluenced by the uncertainties of the system parameters.Finally,the theoretical results are verified by both simulations and experiments on a motion control platform.展开更多
An extended state observer(ESO)-based loop filter is designed for the phase-locked loop(PLL)involved in a disturbed grid-connected converter(GeC).This ESO-based design enhances the performances and robustness of the P...An extended state observer(ESO)-based loop filter is designed for the phase-locked loop(PLL)involved in a disturbed grid-connected converter(GeC).This ESO-based design enhances the performances and robustness of the PLL,and,therefore,improves control performances of the disturbed GeCs.Besides,the ESO-based LF can be applied to PLLs with extra filters for abnormal grid conditions.The unbalanced grid is particularly taken into account for the performance analysis.A tuning approach based on the well-designed PI controller is discussed,which results in a fair comparison with conventional PI-type PLLs.The frequency domain properies are quantitatively analysed with respeet to the control stability and the noises rejection.The frequency domain analysis and simulation results suggesti that the performances of the generated ESO-based controllers are comparable to those of the PI control at low frequency,while have better ability to atenuate high-frequency measurement noises.The phase margin decreases slightly,but remains acceptable.Finally,experimental tests are conducted with a hybrid power hardwarein-the-loop benchmark,in which balanced/unbalanced cases are both explored.The obtained results prove the effectiveness of ESO based PLLs when applied to the disturbed GeC.展开更多
Grid impedance and phase-locked loop(PLL)are critical factors for the stability of the grid-connected inverters(GCIs)in a weak grid.They are the positive feedback control loops formed by PLL in the GCI with grid imped...Grid impedance and phase-locked loop(PLL)are critical factors for the stability of the grid-connected inverters(GCIs)in a weak grid.They are the positive feedback control loops formed by PLL in the GCI with grid impedance.It is prone to GCI instability,especially in the case of the higher PLL bandwidth.A novel impedance-phase and magnitude control strategy is proposed to improve stability of GCI with different grid impedance.Moreover,a detailed design of control loop and parameter calculation for the impedance-phase and magnitude control strategy are introduced.First,PLL output impedance is reshaped to broaden the frequency range of the GCI phase-frequency characteristic curve above the−90°line towards the low-frequency band.In addition,current loop output impedance is reshaped to maintain the phase margin(PM)of the GCI near to 45°.Meanwhile,the magnitude of GCI output impedance is also increased significantly.Stability of the GCI in a weak grid is enhanced by adopting the proposed control strategy.Simulation and experimental results verify the analysis and the proposed method.展开更多
该文研究了电网换相换流器高压直流输电(line commutated converter high voltage direct current,LCC-HVDC)系统逆变侧采用不同锁相环时,锁相环控制回路比例–积分(proportional integral,PI)参数变化对直流控制回路稳定性的影响。首先...该文研究了电网换相换流器高压直流输电(line commutated converter high voltage direct current,LCC-HVDC)系统逆变侧采用不同锁相环时,锁相环控制回路比例–积分(proportional integral,PI)参数变化对直流控制回路稳定性的影响。首先,分别建立了逆变侧锁相环采用滑动平均滤波(mo ving average filter,MAF)和级联延时消去滤波(cascaded delayed signal cancellation,CDSC)的LCC-HVDC小干扰动态模型,并通过电磁暂态仿真验证了该模型的正确性。其次,基于拉普拉斯变换获得系统定电压控制回路的传递函数,利用奈奎斯特稳定判据以及稳定裕度指标分析不同锁相环对定电压控制回路稳定性的影响,并进行了机理分析,同时在PSCAD/EMTDC的电磁暂态模型上进行了验证。最后,进一步在LCC-HVDC工程模型上对该文所得结论的普适性进行了仿真验证。展开更多
针对传统Buck型开关稳压电源环路补偿设计复杂的问题,提出了一种基于数字PID算法进行环路补偿的控制策略,在对Buck型变换器进行建模分析的基础上,加入数字PID算法进行改进,并对改进前后的系统进行建模分析。仿真结果表明,设计系统的相...针对传统Buck型开关稳压电源环路补偿设计复杂的问题,提出了一种基于数字PID算法进行环路补偿的控制策略,在对Buck型变换器进行建模分析的基础上,加入数字PID算法进行改进,并对改进前后的系统进行建模分析。仿真结果表明,设计系统的相位裕度为78.5°,穿越频率为56 kHz,相关参数符合预设。在样机测试阶段,设定输出电压为20 V,空载输出纹波为26 m V,负载调整率等指标满足一般需求,相关实验证明了该方法的可行性,可按需应用于Buck型开关稳压电源场景中,以改善环路及输出稳定性。展开更多
基金This work was supported by the National Key R&D Program of China(No.2018YFA0703800)the National Natural Science Foundation of China(No.U20B2054).
文摘The paper analyzes and compares the phase margins of four active disturbance rejection control(ADRC)designs,which are based on different common-used extended state observers(ESOs)of various orders,for second-order systems.The quantitative results indicate that,besides good dynamic response,ADRC can guarantee enough phase margin.It is also proved that by decreasing the order of ESO,the phase margin can be increased.Furthermore,it is demonstrated that the phase margins of the ADRC-based systems can be almost uninfluenced by the uncertainties of the system parameters.Finally,the theoretical results are verified by both simulations and experiments on a motion control platform.
基金This paper was supported by G2elab,Grenoble INP,University Grenoble Alpes,France and School of Engineering,HES-sO,Valais,Switzerlandfunding provided by Haute Ecole Specialisee de Suisse occidentale(HES-SO)
文摘An extended state observer(ESO)-based loop filter is designed for the phase-locked loop(PLL)involved in a disturbed grid-connected converter(GeC).This ESO-based design enhances the performances and robustness of the PLL,and,therefore,improves control performances of the disturbed GeCs.Besides,the ESO-based LF can be applied to PLLs with extra filters for abnormal grid conditions.The unbalanced grid is particularly taken into account for the performance analysis.A tuning approach based on the well-designed PI controller is discussed,which results in a fair comparison with conventional PI-type PLLs.The frequency domain properies are quantitatively analysed with respeet to the control stability and the noises rejection.The frequency domain analysis and simulation results suggesti that the performances of the generated ESO-based controllers are comparable to those of the PI control at low frequency,while have better ability to atenuate high-frequency measurement noises.The phase margin decreases slightly,but remains acceptable.Finally,experimental tests are conducted with a hybrid power hardwarein-the-loop benchmark,in which balanced/unbalanced cases are both explored.The obtained results prove the effectiveness of ESO based PLLs when applied to the disturbed GeC.
基金supported in part by the Leading talents of scientific and technological innovation in Hunan Province under Grant(No.2019RS3014)the National Natural Science Foundation of China under Grant(No.51907057)。
文摘Grid impedance and phase-locked loop(PLL)are critical factors for the stability of the grid-connected inverters(GCIs)in a weak grid.They are the positive feedback control loops formed by PLL in the GCI with grid impedance.It is prone to GCI instability,especially in the case of the higher PLL bandwidth.A novel impedance-phase and magnitude control strategy is proposed to improve stability of GCI with different grid impedance.Moreover,a detailed design of control loop and parameter calculation for the impedance-phase and magnitude control strategy are introduced.First,PLL output impedance is reshaped to broaden the frequency range of the GCI phase-frequency characteristic curve above the−90°line towards the low-frequency band.In addition,current loop output impedance is reshaped to maintain the phase margin(PM)of the GCI near to 45°.Meanwhile,the magnitude of GCI output impedance is also increased significantly.Stability of the GCI in a weak grid is enhanced by adopting the proposed control strategy.Simulation and experimental results verify the analysis and the proposed method.
文摘该文研究了电网换相换流器高压直流输电(line commutated converter high voltage direct current,LCC-HVDC)系统逆变侧采用不同锁相环时,锁相环控制回路比例–积分(proportional integral,PI)参数变化对直流控制回路稳定性的影响。首先,分别建立了逆变侧锁相环采用滑动平均滤波(mo ving average filter,MAF)和级联延时消去滤波(cascaded delayed signal cancellation,CDSC)的LCC-HVDC小干扰动态模型,并通过电磁暂态仿真验证了该模型的正确性。其次,基于拉普拉斯变换获得系统定电压控制回路的传递函数,利用奈奎斯特稳定判据以及稳定裕度指标分析不同锁相环对定电压控制回路稳定性的影响,并进行了机理分析,同时在PSCAD/EMTDC的电磁暂态模型上进行了验证。最后,进一步在LCC-HVDC工程模型上对该文所得结论的普适性进行了仿真验证。
文摘针对传统Buck型开关稳压电源环路补偿设计复杂的问题,提出了一种基于数字PID算法进行环路补偿的控制策略,在对Buck型变换器进行建模分析的基础上,加入数字PID算法进行改进,并对改进前后的系统进行建模分析。仿真结果表明,设计系统的相位裕度为78.5°,穿越频率为56 kHz,相关参数符合预设。在样机测试阶段,设定输出电压为20 V,空载输出纹波为26 m V,负载调整率等指标满足一般需求,相关实验证明了该方法的可行性,可按需应用于Buck型开关稳压电源场景中,以改善环路及输出稳定性。
