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A Histogram-Based Static Error Correction Technique for Flash ADCs: Implementation
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作者 J Jacob Wikner Armin Jalili +1 位作者 Sayed Masoud Sayedi Rasoul Dehghani 《ZTE Communications》 2012年第1期63-70,共8页
In this paper, we focus on practical issues in implementing a calibration technique for medium-resolution, highspeed flash analogtodigital converters (ADCs). In [1], we theoretically describ the calibration techniqu... In this paper, we focus on practical issues in implementing a calibration technique for medium-resolution, highspeed flash analogtodigital converters (ADCs). In [1], we theoretically describ the calibration technique and perform a behaviorallevel simulation to test its functionality [1]. In this work, we discuss some issues in transistorlevel implementation. The predominant factors that contribute to static errors such as reference generator mismatch and trackandhold (T/H) gain error can be treated as inputreferred offsets of each comparator. Using the proposed calibration technique, these errors can be calibrated with minimal detriment to the dynamic performance of the converter. We simulate a transistorlevel implementation of a 5-bit, 1 GHz ADC in a 1.2 V, 65 nm CMOS process. The results show that DNL can be improved from 2.5 LSB to below 0.7 LSB after calibration, and INL can be improved from 1.6 LSB to below 0.6 LSB after calibration. 展开更多
关键词 Calibration CHOPPING flash ADC pdf generator referencegenerator circuit track and hold circuit
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