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Pseudo-noise preamble based joint frame and frequency synchronization algorithm in OFDM communication systems 被引量:4
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作者 Qingfeng Jing Ming Cheng +2 位作者 Yuping Lu Weizhi Zhong Hongwei Yao 《Journal of Systems Engineering and Electronics》 SCIE EI CSCD 2014年第1期1-9,共9页
Frame and frequency synchronization are essential for orthogonal frequency division multiplexing (OFDM) systems. The frame offset owing to incorrect start point position of the fast Fourier transform (FFT) window,... Frame and frequency synchronization are essential for orthogonal frequency division multiplexing (OFDM) systems. The frame offset owing to incorrect start point position of the fast Fourier transform (FFT) window, and the carrier frequency offset (CFO) due to Doppler frequency shift or the frequency mismatch between the transmitter and receiver oscil ators, can bring severe inter-symbol interference (ISI) and inter-carrier interference (ICI) for the OFDM system. Relying on the relatively good correlation charac-teristic of the pseudo-noise (PN) sequence, a joint frame offset and normalized CFO estimation algorithm based on PN preamble in time domain is developed to realize the frame and frequency synchronization in the OFDM system. By comparison, the perfor-mances of the traditional algorithm and the improved algorithm are simulated under different conditions. The results indicate that the PN preamble based algorithm both in frame offset estimation and CFO estimation is more accurate, resource-saving and robust even under poor channel condition, such as low signal-to-noise ratio (SNR) and large normalized CFO. 展开更多
关键词 orthogonal frequency division multiplexing ofdm frame synchronization carrier frequency offset (CFO) estimation preamble pseudo-noise sequence.
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LDPC Coded TDS-OFDM for PLC Systems
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作者 戴凌龙 符剑 王军 《Tsinghua Science and Technology》 SCIE EI CAS 2010年第3期312-318,共7页
Powerline communications (PLC) have drawn great interest in recent years. However, most PLC standards such as HomePlug AV use the cyclic-prefix OFDM (CP-OFDM) technology. This paper presents a broadband PLC system... Powerline communications (PLC) have drawn great interest in recent years. However, most PLC standards such as HomePlug AV use the cyclic-prefix OFDM (CP-OFDM) technology. This paper presents a broadband PLC system using low density parity check (LDPC) coded time domain synchronous OFDM (TDS-OFDM), whose spectrum efficiency is about 10% higher than that of CP-OFDM. With the same bandwidth and the ability to combat the time delay spread as HomePlug AV, this system can provide a maximum throughput of 199.7 Mbps physical layer data rate. Simulations over the measured practical powerline channel in Beijing, China, show that LDPC in the TDS-OFDM system dramatically improves the bit error rate performance, and verify the feasibility and performance of the TDS-OFDM technology for PLC systems. 展开更多
关键词 powerline communications (PLC) time domain synchronous ofdm (TDS-ofdm low density parity check (LDPC) HomePlug AV channel measurement
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A novel 3780-point FFT processor scheme for the time domain synchronous OFDM system
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作者 Ji-nan LENG Lei XIE +1 位作者 Hui-fang CHEN Kuang WANG 《Journal of Zhejiang University-Science C(Computers and Electronics)》 SCIE EI 2011年第12期1021-1030,共10页
The 3780-point FFT is a main component of the time domain synchronous OFDM (TDS-OFDM) system and the key technology in the Chinese Digital Multimedia/TV Broadcasting-Terrestrial (DMB-T) national standard. Sinc, e ... The 3780-point FFT is a main component of the time domain synchronous OFDM (TDS-OFDM) system and the key technology in the Chinese Digital Multimedia/TV Broadcasting-Terrestrial (DMB-T) national standard. Sinc, e 3780 is not a power of 2, the classical radix-2 or radix-4 FFT algorithm cannot be applied directly. Hence, the Winograd Fourier transform algorithm (WFTA) and the Good-Thomas prime factor algorithm (PFA) are used to implement the 3780-point FFT processor. However, the structure based on WFTA and PFA has a large computational complexity and requires many DSPs in hardware implementation. In this paper, a novel 3780-point FFT processor scheme is proposed, in which a 60x63 iterative WFTA architecture with different mapping methods is imported to replace the PFA architecture, and an optimized CoOrdinate Rotation Digital Computer (CORDIC) module is used for the twiddle factor multiplications. Compared to the traditional scheme, our proposed 3780-point FFT processor scheme reduces the number of multiplications by 45% at the cost of 1% increase in the number of additions. All DSPs are replaced by the optimized CORDIC module and ROM. Simulation results show that the proposed 3780-point FFT processing scheme satisfies the requirement of the DMB-T standard, and is an efficient architecture for the TDS-OFDM system. 展开更多
关键词 3780 CoOrdinate Rotation Digital Computer (CORDIC) Digital Multimedia/TV Broadcasting-Terrestrial (DMB-T) FFT Time domain synchronous ofdm (TDS-ofdm Winograd Fourier transform algorithm (WFTA)
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