Emerging two-dimensional(2D)semiconductors are among the most promising materials for ultra-scaled transistors due to their intrinsic atomic-level thickness.As the stacking process advances,the complexity and cost of ...Emerging two-dimensional(2D)semiconductors are among the most promising materials for ultra-scaled transistors due to their intrinsic atomic-level thickness.As the stacking process advances,the complexity and cost of nanosheet field-effect transistors(NSFETs)and complementary FET(CFET)continue to rise.The 1 nm technology node is going to be based on Si-CFET process according to international roadmap for devices and systems(IRDS)(2022,https://irds.ieee.org/),but not publicly confirmed,indicating that more possibilities still exist.The miniaturization advantage of 2D semiconductors motivates us to explore their potential for reducing process costs while matching the performance of next-generation nodes in terms of area,power consumption and speed.In this study,a comprehensive framework is built.A set of MoS2 NSFETs were designed and fabricated to extract the key parameters and performances.And then for benchmarking,the sizes of 2D-NSFET are scaled to a extent that both of the Si-CFET and 2D-NSFET have the same average device footprint.Under these conditions,the frequency of ultra-scaled 2D-NSFET is found to improve by 36%at a fixed power consumption.This work verifies the feasibility of replacing silicon-based CFETs of 1 nm node with 2D-NSFETs and proposes a 2D technology solution for 1 nm nodes,i.e.,“2D eq 1 nm”nodes.At the same time,thanks to the lower characteristic length of 2D semiconductors,the miniaturized 2D-NSFET achieves a 28%frequency increase at a fixed power consumption.Further,developing a standard cell library,these devices obtain a similar trend in 16-bit RISC-V CPUs.This work quantifies and highlights the advantages of 2D semiconductors in advanced nodes,offering new possibilities for the application of 2D semiconductors in high-speed and low-power integrated circuits.展开更多
Correction to:Nano-Micro Letters(2025)17:191 https://doi.org/10.1007/s40820-025-01702-7 Following the publication of the original article[1],the authors reported an error in Fig.3(b),and the figure legend was reversed...Correction to:Nano-Micro Letters(2025)17:191 https://doi.org/10.1007/s40820-025-01702-7 Following the publication of the original article[1],the authors reported an error in Fig.3(b),and the figure legend was reversed.The correct Fig.3 has been provided in this orrection.展开更多
基金supported in part by STI 2030-Major Projects under Grant 2022ZD0209200in part by Beijing Natural Science Foundation-Xiaomi Innovation Joint Fund(L233009)+4 种基金in part by National Natural Science Foundation of China under Grant No.62374099in part by the Tsinghua-Toyota Joint Research Fundin part by the Daikin Tsinghua Union Programin part by Independent Research Program of School of Integrated Circuits,Tsinghua UniversityThis work was also sponsored by CIE-Tencent Robotics X Rhino-Bird Focused Research Program.
文摘Emerging two-dimensional(2D)semiconductors are among the most promising materials for ultra-scaled transistors due to their intrinsic atomic-level thickness.As the stacking process advances,the complexity and cost of nanosheet field-effect transistors(NSFETs)and complementary FET(CFET)continue to rise.The 1 nm technology node is going to be based on Si-CFET process according to international roadmap for devices and systems(IRDS)(2022,https://irds.ieee.org/),but not publicly confirmed,indicating that more possibilities still exist.The miniaturization advantage of 2D semiconductors motivates us to explore their potential for reducing process costs while matching the performance of next-generation nodes in terms of area,power consumption and speed.In this study,a comprehensive framework is built.A set of MoS2 NSFETs were designed and fabricated to extract the key parameters and performances.And then for benchmarking,the sizes of 2D-NSFET are scaled to a extent that both of the Si-CFET and 2D-NSFET have the same average device footprint.Under these conditions,the frequency of ultra-scaled 2D-NSFET is found to improve by 36%at a fixed power consumption.This work verifies the feasibility of replacing silicon-based CFETs of 1 nm node with 2D-NSFETs and proposes a 2D technology solution for 1 nm nodes,i.e.,“2D eq 1 nm”nodes.At the same time,thanks to the lower characteristic length of 2D semiconductors,the miniaturized 2D-NSFET achieves a 28%frequency increase at a fixed power consumption.Further,developing a standard cell library,these devices obtain a similar trend in 16-bit RISC-V CPUs.This work quantifies and highlights the advantages of 2D semiconductors in advanced nodes,offering new possibilities for the application of 2D semiconductors in high-speed and low-power integrated circuits.
基金supported in part by STI 2030-Major Projects under Grant 2022ZD0209200in part by Beijing Natural Science Foundation-Xiaomi Innovation Joint Fund (L233009)+4 种基金in part by National Natural Science Foundation of China under Grant No. 62374099in part by the Tsinghua-Toyota Joint Research Fundin part by the Daikin Tsinghua Union Programin part by Independent Research Program of School of Integrated Circuits,Tsinghua Universitysponsored by CIE-Tencent Robotics X Rhino-Bird Focused Research Program
文摘Correction to:Nano-Micro Letters(2025)17:191 https://doi.org/10.1007/s40820-025-01702-7 Following the publication of the original article[1],the authors reported an error in Fig.3(b),and the figure legend was reversed.The correct Fig.3 has been provided in this orrection.
