On the basis of a detailed discussion of the development of total ionizing dose （TID） effect model, a new commercial-model-independent TID modeling approach for partially depleted silicon-on-insulator metal-oxide- s...On the basis of a detailed discussion of the development of total ionizing dose （TID） effect model, a new commercial-model-independent TID modeling approach for partially depleted silicon-on-insulator metal-oxide- semiconductor field effect transistors is developed. An exponential approximation is proposed to simplify the trap charge calculation. Irradiation experiments with 60Co gamma rays for IO and core devices are performed to validate the simulation results. An excellent agreement of measurement with the simulation results is observed.展开更多
An analytical model has been developed to study inversion layer quantization in the ultra thin oxide MOS （metal oxide semiconductor） structures using variation and triangular well approaches.Accurate modeling of the...An analytical model has been developed to study inversion layer quantization in the ultra thin oxide MOS （metal oxide semiconductor） structures using variation and triangular well approaches.Accurate modeling of the inversion charge density using the continuous surface potential equations has been done.No approximation has been taken to model the inversion layer quantization process.The results show that the variation approach describes inversion layer quantization process accurately as it matches well with the BSIM 5 （Berkeley short channel insulated gate field effect transistor model 5） results more closely compared with triangular well approach.展开更多
A one-dimensional continuous analytic potential solution to a generic oxide-silicon^xide system is developed. With the analytic solution, the potential distribution in the silicon film is predicted. A physics-based re...A one-dimensional continuous analytic potential solution to a generic oxide-silicon^xide system is developed. With the analytic solution, the potential distribution in the silicon film is predicted. A physics-based relation between surface potentials is also derived and then applied to the generic oxide-silicon-oxide metal oxide-semiconductor field-effect transistors （MOSFETs） for the calculation of surface potentials展开更多
With a reduction in transistor dimensions to the nanoscale regime of 45 nm or less, quantum mechanical effects begin to reveal themselves and have an impact on key device performance parameters. As a result, in order ...With a reduction in transistor dimensions to the nanoscale regime of 45 nm or less, quantum mechanical effects begin to reveal themselves and have an impact on key device performance parameters. As a result, in order to develop simulation tools that can be used for the design of nanoscale transistors in the future, new theories and modelling methodologies must be developed that properly and effectively capture the physics of quantum transport. An artificial neural network(ANN) is used in this paper to examine nanoscale CMOS circuits and predict the performance parameters of CMOS-based digital inverters for a temperature range of 300 K to 400 K. The training algorithm included three hidden layers with sizes of 20, 10, and 8, as well as a function fitting ANN with Bayesian Backpropagation Regularization. Further, simulation through HSPICE using Predictive Technology Model(PTM) nominal parameters has been done to compare with ANN(trained using an analytical model) results. The obtained results lie within the acceptable range of 1%-10%. Moreover, it has also been demonstrated that the ANN simulation provides a speed improvement of around 85 % over the HSPICE simulation, and that it can be easily integrated into software tools for designing and simulating complicated CMOS logic circuits.展开更多
Thisworkpresentsahighlyefficientapproachforbroadbandmodelingofmillimeter-waveCMOSFETs with gate width scalability by using pre-modeled cells. Only a few devices with varied gate width are required to be measured and m...Thisworkpresentsahighlyefficientapproachforbroadbandmodelingofmillimeter-waveCMOSFETs with gate width scalability by using pre-modeled cells. Only a few devices with varied gate width are required to be measured and modeled with fixed models, and later used as pre-modeled cells. Then a target device with the desired gate width is constructed by choosing appropriate cells and connecting them with a wiring network. The corresponding scalable model is constructed by incorporating the fixed models of the cells used in the target device and the scalable model of the connection wires. The proposed approach is validated by experiments on 65-nm CMOS process up to 40 GHz and across a wide range of gate widths.展开更多
基金Supported by the National Natural Science Foundation of China under Grant Nos 61404151 and 61574153
文摘On the basis of a detailed discussion of the development of total ionizing dose （TID） effect model, a new commercial-model-independent TID modeling approach for partially depleted silicon-on-insulator metal-oxide- semiconductor field effect transistors is developed. An exponential approximation is proposed to simplify the trap charge calculation. Irradiation experiments with 60Co gamma rays for IO and core devices are performed to validate the simulation results. An excellent agreement of measurement with the simulation results is observed.
文摘An analytical model has been developed to study inversion layer quantization in the ultra thin oxide MOS （metal oxide semiconductor） structures using variation and triangular well approaches.Accurate modeling of the inversion charge density using the continuous surface potential equations has been done.No approximation has been taken to model the inversion layer quantization process.The results show that the variation approach describes inversion layer quantization process accurately as it matches well with the BSIM 5 （Berkeley short channel insulated gate field effect transistor model 5） results more closely compared with triangular well approach.
基金Project supported by the National Natural Science Foundation of China (Grant Nos.60876027 and 60976066)the National Science Fund for Distinguished Young Scholars of China (Grant No.60925015)
文摘A one-dimensional continuous analytic potential solution to a generic oxide-silicon^xide system is developed. With the analytic solution, the potential distribution in the silicon film is predicted. A physics-based relation between surface potentials is also derived and then applied to the generic oxide-silicon-oxide metal oxide-semiconductor field-effect transistors （MOSFETs） for the calculation of surface potentials
文摘With a reduction in transistor dimensions to the nanoscale regime of 45 nm or less, quantum mechanical effects begin to reveal themselves and have an impact on key device performance parameters. As a result, in order to develop simulation tools that can be used for the design of nanoscale transistors in the future, new theories and modelling methodologies must be developed that properly and effectively capture the physics of quantum transport. An artificial neural network(ANN) is used in this paper to examine nanoscale CMOS circuits and predict the performance parameters of CMOS-based digital inverters for a temperature range of 300 K to 400 K. The training algorithm included three hidden layers with sizes of 20, 10, and 8, as well as a function fitting ANN with Bayesian Backpropagation Regularization. Further, simulation through HSPICE using Predictive Technology Model(PTM) nominal parameters has been done to compare with ANN(trained using an analytical model) results. The obtained results lie within the acceptable range of 1%-10%. Moreover, it has also been demonstrated that the ANN simulation provides a speed improvement of around 85 % over the HSPICE simulation, and that it can be easily integrated into software tools for designing and simulating complicated CMOS logic circuits.
基金Project supported by the Major State Basic Research Development Program of China(No.2010CB327403)
文摘Thisworkpresentsahighlyefficientapproachforbroadbandmodelingofmillimeter-waveCMOSFETs with gate width scalability by using pre-modeled cells. Only a few devices with varied gate width are required to be measured and modeled with fixed models, and later used as pre-modeled cells. Then a target device with the desired gate width is constructed by choosing appropriate cells and connecting them with a wiring network. The corresponding scalable model is constructed by incorporating the fixed models of the cells used in the target device and the scalable model of the connection wires. The proposed approach is validated by experiments on 65-nm CMOS process up to 40 GHz and across a wide range of gate widths.
