By using the pulsed laser single event effect facility and electro-static discharge （ESD） test system, the characteristics of the ＂high current＂, relation with external stimulus and relevance to impacted modes of ...By using the pulsed laser single event effect facility and electro-static discharge （ESD） test system, the characteristics of the ＂high current＂, relation with external stimulus and relevance to impacted modes of single event latch-up （SEL） and transient-induced latch-up （TLU） are studied, respectively, for a 12-bit complementary metal--oxide semiconductor （CMOS） analog-to-digital converter. Furthermore, the sameness and difference in physical mechanism between ＂high current＂ induced by SEL and that by TLU are disclosed in this paper. The results show that the minority carrier diffusion in the PNPN structure of the CMOS device which initiates the active parasitic NPN and PNP transistors is the common reason for the ＂high current＂ induced by SEL and for that by TLU, However, for SEL, the minority carder diffusion is induced by the ionizing radiation, and an underdamped sinusoidal voltage on the supply node （the ground node） is the cause of the minority carrier diffusion for TLU.展开更多
The latch-up effect induced by high-power microwave（HPM） in complementary metal–oxide–semiconductor（CMOS） inverter is investigated in simulation and theory in this paper. The physical mechanisms of excess carrie...The latch-up effect induced by high-power microwave（HPM） in complementary metal–oxide–semiconductor（CMOS） inverter is investigated in simulation and theory in this paper. The physical mechanisms of excess carrier injection and HPM-induced latch-up are proposed. Analysis on upset characteristic under pulsed wave reveals increasing susceptibility under shorter-width pulsed wave which satisfies experimental data, and the dependence of upset threshold on pulse repetitive frequency（PRF） is believed to be due to the accumulation of excess carriers. Moreover, the trend that HPMinduced latch-up is more likely to happen in shallow-well device is proposed.Finally, the process of self-recovery which is ever-reported in experiment with its correlation with supply voltage and power level is elaborated, and the conclusions are consistent with reported experimental results.展开更多
Considering the phenomenon of Latch-up in CMOS device,some patterns of manifestation about Latch-up in electronic system are analyzed with three actual circuits,meanwhile the correlative solving methods are also provi...Considering the phenomenon of Latch-up in CMOS device,some patterns of manifestation about Latch-up in electronic system are analyzed with three actual circuits,meanwhile the correlative solving methods are also provided. To avoid Latch-up,some general principles are proposed. The analyzing and solving processes derived from practical system design are verified simple and ef-fective in large number of products,and to some extend have general reference value in anti-latch-up design of application systems.展开更多
The temperature dependence of the latch-up effects in a CMOS inverter based on 0.5 μm technology caused by high power microwave （HPM） is studied. The malfunction and power supply current characteristics are reveale...The temperature dependence of the latch-up effects in a CMOS inverter based on 0.5 μm technology caused by high power microwave （HPM） is studied. The malfunction and power supply current characteristics are revealed and adopted as the latch-up criteria. The thermal effect is shown and analyzed in detail. CMOS in- verters operating at high ambient temperature are confirmed to be more susceptible to HPM, which is verified by experimental results from previous literature. Besides the dependence of the latch-up triggering power P on the ambient temperature T follows the power-law equation P = ATβ. Meanwhile, the ever reported latch-up delay time characteristic is interpreted to be affected by the temperature distribution. In addition, it is found that the power threshold increases with the decrease in pulse width but the degree of change with a certain pulse width is constant at different ambient temperatures. Also, the energy absorbed to cause latch-up at a certain temperature is basically sustained at a constant value.展开更多
The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail ESD（electro-static discharge） clamp circuits.In order to eliminate latch-up risk,this work pr...The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail ESD（electro-static discharge） clamp circuits.In order to eliminate latch-up risk,this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current.The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.展开更多
星载抗辐射多频多模导航器件单粒子效应(SEE)数据获取为器件能否在轨可靠使用提供重要参考。在介绍公司自研导航器件组成结构和抗辐照加固设计的基础上,通过设计专用试验板,在FPGA上进行DFT-SCAN、MBIST向量测试。利用重离子加速器完成...星载抗辐射多频多模导航器件单粒子效应(SEE)数据获取为器件能否在轨可靠使用提供重要参考。在介绍公司自研导航器件组成结构和抗辐照加固设计的基础上,通过设计专用试验板,在FPGA上进行DFT-SCAN、MBIST向量测试。利用重离子加速器完成空间单粒子辐照的地面模拟实验,以此确定导航器件的单粒子数据。通过实验数据计算得到导航器件SEE指标数据:抗单粒子锁定LET≥81.4 MeV·cm^(2)/mg,在GEO轨道、ADAMS 90%最坏环境模型、3 mm Al屏蔽条件下,器件SCAN链模式单粒子翻转概率为6.80×10^(-8)次/(天·位),SRAM模式单粒子翻转概率为5.61×10^(-11)次/(天·位),单粒子功能中断概率为5.75×10^(-5)次/(天·器件),为在轨航天器导航接收机使用提供依据和参考。展开更多
瞬态抑制器(Transient Voltage Suppressor, TVS)是一类能将单个或连续的瞬态高电压电信号迅速抑制在安全范围内并保护与之相连电子系统的半导体器件的统称,被广泛应用于各类敏感电子系统的保护电路中。首先,结合前期研究成果,概括目前...瞬态抑制器(Transient Voltage Suppressor, TVS)是一类能将单个或连续的瞬态高电压电信号迅速抑制在安全范围内并保护与之相连电子系统的半导体器件的统称,被广泛应用于各类敏感电子系统的保护电路中。首先,结合前期研究成果,概括目前TVS器件在机载雷击与电磁脉冲防护方面的发展与技术瓶颈。其次,根据TVS器件能量等级、电压等级以及工作机理的差异,对不同TVS器件技术进行分类与总结,梳理TVS器件设计中的各类新结构与工艺创新。最后,针对未来航空航天设备更高的防护要求,从芯片材料、工艺与封装角度进行技术展望,提出可能的发展方向。展开更多
An improved on-chip CMOS astable multivibrator is proposed, which overcomes the shortcomings of the traditional one that the signal duty-cycle is depending on model parameters, and generates stable clock signal with d...An improved on-chip CMOS astable multivibrator is proposed, which overcomes the shortcomings of the traditional one that the signal duty-cycle is depending on model parameters, and generates stable clock signal with duty-cycle equaling 50%. The latch-up effect has been prevented on the improved circuit. It is extremely important that all the excellent performances of the improved astable multivibrator have been achieved with a dynamic power consumption equaling its predecessor one. The advantage of the structure has been verified by SPICE simulation.展开更多
基金Project supported by the National Natural Science Foundation of China(Grant No.41304148)
文摘By using the pulsed laser single event effect facility and electro-static discharge （ESD） test system, the characteristics of the ＂high current＂, relation with external stimulus and relevance to impacted modes of single event latch-up （SEL） and transient-induced latch-up （TLU） are studied, respectively, for a 12-bit complementary metal--oxide semiconductor （CMOS） analog-to-digital converter. Furthermore, the sameness and difference in physical mechanism between ＂high current＂ induced by SEL and that by TLU are disclosed in this paper. The results show that the minority carrier diffusion in the PNPN structure of the CMOS device which initiates the active parasitic NPN and PNP transistors is the common reason for the ＂high current＂ induced by SEL and for that by TLU, However, for SEL, the minority carder diffusion is induced by the ionizing radiation, and an underdamped sinusoidal voltage on the supply node （the ground node） is the cause of the minority carrier diffusion for TLU.
基金Project supported by the Open Fund of Key Laboratory of Complex Electromagnetic Environment Science and Technology,China Academy of Engineering Physics(Grant No.2015-0214.XY.K)
文摘The latch-up effect induced by high-power microwave（HPM） in complementary metal–oxide–semiconductor（CMOS） inverter is investigated in simulation and theory in this paper. The physical mechanisms of excess carrier injection and HPM-induced latch-up are proposed. Analysis on upset characteristic under pulsed wave reveals increasing susceptibility under shorter-width pulsed wave which satisfies experimental data, and the dependence of upset threshold on pulse repetitive frequency（PRF） is believed to be due to the accumulation of excess carriers. Moreover, the trend that HPMinduced latch-up is more likely to happen in shallow-well device is proposed.Finally, the process of self-recovery which is ever-reported in experiment with its correlation with supply voltage and power level is elaborated, and the conclusions are consistent with reported experimental results.
基金A Project Supported by Scientific Research Fund of Zhejiang Provincial Education Department. Project name:Research and Design on Network Communication Controller for Fiber Cable TV.Project number:20061473.
文摘Considering the phenomenon of Latch-up in CMOS device,some patterns of manifestation about Latch-up in electronic system are analyzed with three actual circuits,meanwhile the correlative solving methods are also provided. To avoid Latch-up,some general principles are proposed. The analyzing and solving processes derived from practical system design are verified simple and ef-fective in large number of products,and to some extend have general reference value in anti-latch-up design of application systems.
基金Project supported by the National Natural Science Foundation of China(No.60776034)the State Key Development Program for Basic Research of China(No.2014CC339900)
文摘The temperature dependence of the latch-up effects in a CMOS inverter based on 0.5 μm technology caused by high power microwave （HPM） is studied. The malfunction and power supply current characteristics are revealed and adopted as the latch-up criteria. The thermal effect is shown and analyzed in detail. CMOS in- verters operating at high ambient temperature are confirmed to be more susceptible to HPM, which is verified by experimental results from previous literature. Besides the dependence of the latch-up triggering power P on the ambient temperature T follows the power-law equation P = ATβ. Meanwhile, the ever reported latch-up delay time characteristic is interpreted to be affected by the temperature distribution. In addition, it is found that the power threshold increases with the decrease in pulse width but the degree of change with a certain pulse width is constant at different ambient temperatures. Also, the energy absorbed to cause latch-up at a certain temperature is basically sustained at a constant value.
基金Project supported by the Natural Science Foundation of Jiangsu Province (No.BK2011059)the Program for New Century Excellent Talent in University (No.NCET-10-0331)
文摘The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail ESD（electro-static discharge） clamp circuits.In order to eliminate latch-up risk,this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current.The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.
文摘星载抗辐射多频多模导航器件单粒子效应(SEE)数据获取为器件能否在轨可靠使用提供重要参考。在介绍公司自研导航器件组成结构和抗辐照加固设计的基础上,通过设计专用试验板,在FPGA上进行DFT-SCAN、MBIST向量测试。利用重离子加速器完成空间单粒子辐照的地面模拟实验,以此确定导航器件的单粒子数据。通过实验数据计算得到导航器件SEE指标数据:抗单粒子锁定LET≥81.4 MeV·cm^(2)/mg,在GEO轨道、ADAMS 90%最坏环境模型、3 mm Al屏蔽条件下,器件SCAN链模式单粒子翻转概率为6.80×10^(-8)次/(天·位),SRAM模式单粒子翻转概率为5.61×10^(-11)次/(天·位),单粒子功能中断概率为5.75×10^(-5)次/(天·器件),为在轨航天器导航接收机使用提供依据和参考。
文摘瞬态抑制器(Transient Voltage Suppressor, TVS)是一类能将单个或连续的瞬态高电压电信号迅速抑制在安全范围内并保护与之相连电子系统的半导体器件的统称,被广泛应用于各类敏感电子系统的保护电路中。首先,结合前期研究成果,概括目前TVS器件在机载雷击与电磁脉冲防护方面的发展与技术瓶颈。其次,根据TVS器件能量等级、电压等级以及工作机理的差异,对不同TVS器件技术进行分类与总结,梳理TVS器件设计中的各类新结构与工艺创新。最后,针对未来航空航天设备更高的防护要求,从芯片材料、工艺与封装角度进行技术展望,提出可能的发展方向。
文摘An improved on-chip CMOS astable multivibrator is proposed, which overcomes the shortcomings of the traditional one that the signal duty-cycle is depending on model parameters, and generates stable clock signal with duty-cycle equaling 50%. The latch-up effect has been prevented on the improved circuit. It is extremely important that all the excellent performances of the improved astable multivibrator have been achieved with a dynamic power consumption equaling its predecessor one. The advantage of the structure has been verified by SPICE simulation.
