An improved rate distortion optimization （RDO） algorithm in JPEG2000 is proposed. The proposed algorithm is suitable for integrated circuit （IC） implementation and can reduce 30% computational cost. A hardware arc...An improved rate distortion optimization （RDO） algorithm in JPEG2000 is proposed. The proposed algorithm is suitable for integrated circuit （IC） implementation and can reduce 30% computational cost. A hardware architecture which includes control unit, memory, divider, data converter is also given to implement the algorithm. The circuit based on the improved algorithm is tested on FPGAs and integrated in a JPG2000 chip codec core.展开更多
In order to solve the problem that the testing cost of the three-dimensional integrated circuit(3D IC)is too high,an optimal stacking order scheme is proposed to reduce the mid-bond test cost.A new testing model is bu...In order to solve the problem that the testing cost of the three-dimensional integrated circuit(3D IC)is too high,an optimal stacking order scheme is proposed to reduce the mid-bond test cost.A new testing model is built with the general consideration of both the test time for automatic test equipment(ATE)and manufacturing failure factors.An algorithm for testing cost and testing order optimization is proposed,and the minimum testing cost and optimized stacking order can be carried out by taking testing bandwidth and testing power as constraints.To prove the influence of the optimal stacking order on testing costs,two baselines stacked in sequential either in pyramid type or in inverted pyramid type are compared.Based on the benchmarks from ITC 02,experimental results show that for a 5-layer 3D IC,under different constraints,the optimal stacking order can reduce the test costs on average by 13%and 62%,respectively,compared to the pyramid type and inverted pyramid type.Furthermore,with the increase of the stack size,the test costs of the optimized stack order can be decreased.展开更多
Many 3D IC applications such as MEMS and RF systems require Through-Silicon Via （TSV） with operations for high-speed vertical communication. In this paper, we introduce a novel air-gap coaxial TSV that is suiTab, fo...Many 3D IC applications such as MEMS and RF systems require Through-Silicon Via （TSV） with operations for high-speed vertical communication. In this paper, we introduce a novel air-gap coaxial TSV that is suiTab, for such RF applications. Firstly, the detailed fabrication process is described to explain how to acquire such a structure. Then, an Resistor Inductance Conductance Capacitance （RLGC） model is developed to profile the transverse electromagnetic field effect of the proposed air-gap TSV. The model is further verified by a 3D field solver program through the S-parameter comparison. With reference to the numerically simulated results, this analytical model delivers a maximum deviation of less than 6%0, on the conditions of varying diameters, outer to inner radius ratios, and SU-8 central angles, etc. Taking advantages of scalability of the model, a number of air-gap-based TSV designs are simulated, providing 1.6-4.0 times higher bandwidth than the con- ventional coaxial TSVs and leading to an efficient high frequency vertical RF interconnection solution for 3D ICs.展开更多
Hardware implementation of Linear Feedback Shift Register (LFSR) plays a great and very important role in communication systems, and in many security devices. In this paper, a design of LFSR with offset mask has been ...Hardware implementation of Linear Feedback Shift Register (LFSR) plays a great and very important role in communication systems, and in many security devices. In this paper, a design of LFSR with offset mask has been presented, for Direct Sequence Code Division Multiple Access (DS-CDMA) applications. Integrated electronic components have been used. An accessible model facilitating the synthesis on Printed Circuit Boards (PCB) and implementation on Field Programmable Gate Array (FPGA) is offered. In addition, a temporal and spectral analysis of the circuit is performed in order to validate the design. This latter facilitates the generation of pseudo-random codes based on LFSR and their integration into electronic systems.展开更多
The novel integrated circuit (IC) temperature sensor presented in this paper works similarly as a two terminal Zener, has breakdown voltage directly proportional to Kelvin temperature at 10 mV/℃, with typical error ...The novel integrated circuit (IC) temperature sensor presented in this paper works similarly as a two terminal Zener, has breakdown voltage directly proportional to Kelvin temperature at 10 mV/℃, with typical error of less than ±1.0℃ over a temperature range from -50℃ to +125℃. In addition to all the features that conventional IC temperature sensors have, the new device also has very low static power dissipation ( 0.5 mW ) , low output impedance ( less than 1Ω), excellent stability, high reproducibility, and high precision. The sensor's circuit design and layout are discussed in detail. Applications of the sensor include almost any type of temperature sensing over the range of -50℃-+125℃. The low impedance and linear output of the device make interfacing the readout or control circuitry especially easy. Due to the excellent performance and low cost of this sensor, more applications of the sensor over wide temperature range are expected.展开更多
With the rapid development of integrated circuit(IC)technology,reusable intelligent property(IP)core design is widely valued by the industry.Based on the in-depth study of the functional characteristics of advanced mi...With the rapid development of integrated circuit(IC)technology,reusable intelligent property(IP)core design is widely valued by the industry.Based on the in-depth study of the functional characteristics of advanced microcontroller bus architecture(AMBA),a design scheme of IP core is presented,and it is divided into the functional modules,and the structural design of the IP core is completed.The relationship between the internal modules of the IP core is clarified,and the top-down design method is used to build the internal architecture of the IP core.The IP core interface module,register module,baud rate module,transmit module,receive module,and interrupt module are designed in detail by using Verilog language.The simulation results show that the designed IP core supports serial peripheral interface(SPI)protocol,the function coverage of IP core reaches 100%,the maximum working frequency reaches 200 MHz,and the resource occupancy rate is less than 15%.The reusable IP core can support multiple data formats,multiple timing transmission modes,and master/slave operation modes,reducing the resource consumption of hardware circuits and having stronger applicability.展开更多
This paper proposes a redundant network communication structure for the patient integrated circuit(IC)card payment system in a hospital information system(HIS),compares it with the network structure of normal hospital...This paper proposes a redundant network communication structure for the patient integrated circuit(IC)card payment system in a hospital information system(HIS),compares it with the network structure of normal hospital IC card system,and calculates the reliabilities of the related communications like the RS485communication and the Ethernet communication.The new structure can efectively promote the reliability of the hospital operation and ensure the payment collection when the Ethernet network is broken.The system is applied to a local hospital and the cost-performance rate is satisfactory during the application.展开更多
This Special Issue includes five papers from the 2024 IEEE International Conference on Integrated Circuits Technologies and Applications(ICTA),held in Hangzhou,Zhejiang,China,from October 25 to 27,2024.ICTA is an IEEE...This Special Issue includes five papers from the 2024 IEEE International Conference on Integrated Circuits Technologies and Applications(ICTA),held in Hangzhou,Zhejiang,China,from October 25 to 27,2024.ICTA is an IEEE flagship conference in the field of integrated circuits(ICs)in China,providing a platform for the presentation and exchange of the latest technical achievements and fostering cross-discipline collaboration in IC designs,technologies,and applications within the rapidly evolving technical community.展开更多
Monolithic three-dimensional integrated circuits(M3D ICs)have emerged as an innovative solution to overcome the limitations of traditional 2D scaling,offering improved performance,reduced power consumption,and enhance...Monolithic three-dimensional integrated circuits(M3D ICs)have emerged as an innovative solution to overcome the limitations of traditional 2D scaling,offering improved performance,reduced power consumption,and enhanced functionality.Inter-layer vias(ILVs),crucial components of M3D ICs,provide vertical connectivity between layers but are susceptible to manufacturing and operational defects,such as stuck-at faults(SAFs),shorts,and opens,which can compromise system reliability.These challenges necessitate advanced built-in self-test(BIST)methodologies to ensure robust fault detection and localization while minimizing the testing overhead.In this paper,we introduce a novel BIST architecture tailored to efficiently detect ILV defects,particularly in irregularly positioned ILVs,and approximately localize them within clusters,using a walking pattern approach.In the proposed BIST framework,ILVs are grouped according to the probability of fault occurrence,enabling efficient detection of all SAFs and bridging faults(BFs)and most multiple faults within each cluster.This strategy empowers designers to fine-tune fault coverage,localization precision,and test duration to meet specific design requirements.The new BIST method addresses a critical shortcoming of existing solutions by significantly reducing the number of test configurations and overall test time using multiple ILV clusters.The method also enhances efficiency in terms of area and hardware utilization,particularly for larger circuit benchmarks.For instance,in the LU32PEENG benchmark,where ILVs are divided into 64 clusters,the power,area,and hardware overheads are minimized to 0.82%,1.03%,and 1.14%,respectively.展开更多
The majority of microelectromechanical system(MEMS)devices must be combined with integrated circuits(ICs)for operation in larger electronic systems.While MEMS transducers sense or control physical,optical or chemical ...The majority of microelectromechanical system(MEMS)devices must be combined with integrated circuits(ICs)for operation in larger electronic systems.While MEMS transducers sense or control physical,optical or chemical quantities,ICs typically provide functionalities related to the signals of these transducers,such as analog-to-digital conversion,amplification,filtering and information processing as well as communication between the MEMS transducer and the outside world.Thus,the vast majority of commercial MEMS products,such as accelerometers,gyroscopes and micro-mirror arrays,are integrated and packaged together with ICs.There are a variety of possible methods of integrating and packaging MEMS and IC components,and the technology of choice strongly depends on the device,the field of application and the commercial requirements.In this review paper,traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed.These include approaches based on the hybrid integration of multiple chips(multi-chip solutions)as well as system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques.These are important technological building blocks for the‘More-Than-Moore’paradigm described in the International Technology Roadmap for Semiconductors.In this paper,the various approaches are categorized in a coherent manner,their merits are discussed,and suitable application areas and implementations are critically investigated.The implications of the different MEMS and IC integration approaches for packaging,testing and final system costs are reviewed.展开更多
In response to the growing complexity and performance of integrated circuit(IC),there is an urgent need to enhance the testing and stability of IC test equipment.A method was proposed to predict equipment stability us...In response to the growing complexity and performance of integrated circuit(IC),there is an urgent need to enhance the testing and stability of IC test equipment.A method was proposed to predict equipment stability using the upper side boundary value of normal distribution.Initially,the K-means clustering algorithm classifies and analyzes sample data.The accuracy of this boundary value is compared under two common confidence levels to select the optimal threshold.A range is then defined to categorize unqualified test data.Through experimental verification,the method achieves the purpose of measuring the stability of qualitative IC equipment through a deterministic threshold value and judging the stability of the equipment by comparing the number of unqualified data with the threshold value,which realizes the goal of long-term operation monitoring and stability analysis of IC test equipment.展开更多
Traditional planar inductors in Radio Frequency （RF） Integrated Circuits （ICs） are plagued by large areas, low quality, and low frequencies. This paper describes a magnetic-based CMOS-compatible RF in- ductor. Mag...Traditional planar inductors in Radio Frequency （RF） Integrated Circuits （ICs） are plagued by large areas, low quality, and low frequencies. This paper describes a magnetic-based CMOS-compatible RF in- ductor. Magnetic-core inductors with various ferrite-filled structures, spiral structures, and magnetic material permeabilities were simulated to show that this inductor greatly improves the inductance by up to 97% and quality factor by 18.6% over a multi-GHz frequency range. The results indicate that the inductor is a very promising and viable solution to realize miniature, high quality, and high frequency on-chip inductors for high-end RF ICs.展开更多
Electrostatic discharge （ESD） induced parasitic effects have serious impacts on performance of radio frequency （RF） integrated circuits （IC）. This paper discusses a comprehensive noise analysis procedure for ESD...Electrostatic discharge （ESD） induced parasitic effects have serious impacts on performance of radio frequency （RF） integrated circuits （IC）. This paper discusses a comprehensive noise analysis procedure for ESD protection structures and their negative influences on RF ICs. Noise figures （NFs） of commonly used ESD protection structures and their impacts on a single-chip 5.5 GHz low-noise amplifier （LNA） circuit were depicted. A design example in 0.18 μm SiGe BiCMOS was presented. Measurement results confirm that significant noise degradation occurs in the LNA circuit due to ESD-induced noise effects. A practical design procedure for ESD-protected RF ICs is provided for real-world RF IC optimization.展开更多
This Special Issue is dedicated to the selected papers from the 2023 IEEE International Conference on Integrated Circuits Technologies and Applications(ICTA),held in Hefei,Anhui,China,from October 27 to 29,2023.ICTA i...This Special Issue is dedicated to the selected papers from the 2023 IEEE International Conference on Integrated Circuits Technologies and Applications(ICTA),held in Hefei,Anhui,China,from October 27 to 29,2023.ICTA is an IEEE flagship conference in the field of integrated circuits(ICs)in China,providing a platform for the presentation and exchange of the latest technical achievements and fostering cross-discipline collaboration in IC designs,technologies,and applications within the rapidly evolving technical community.展开更多
This paper presents a fully customised integrated gate commutated thyristor(IGCT)gate driver monolithic integrated circuit(GDMIC),aiming to address the many shortcomings of traditional IGCT gate driver units composed ...This paper presents a fully customised integrated gate commutated thyristor(IGCT)gate driver monolithic integrated circuit(GDMIC),aiming to address the many shortcomings of traditional IGCT gate driver units composed of discrete components,such as the excessive number of components,low reliability,and complex development processes.The current-source driving characteristics of IGCTs pose significant technical challenges for developing fully customised integrated circuits(IC).The customised requirements of IGCT gate driver chips under various operating conditions are explored regarding functional module division,power sequencing,and chip parameter specifications.However,existing high-side(HS)driver methods exhibit limitations in functional monolithic integration and bipolar complementary metal-oxide-semiconductor compat-ibility.To address these challenges,a novel HS driving topology based on floating linear regulators is proposed.It can achieve synchronised control of multi-channel floating power transistors while supporting 100%duty cycle continuous conduction.The pro-posed GDMIC reduces the three independent HS power supplies to a single multiplexed topology,significantly decreasing circuit complexity.Experimental results validate the feasibility and performance of a 4-inch gate driver prototype based on IGCT current-source management IC,demonstrating significant advantages in reducing the number of components,enhancing device reliability,and simplifying development.The proposed GDMIC offers an innovative development path for future high-power IGCT drivers.展开更多
This paper presents a new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters （ADC）. The new offset averaging design technique takes full advantage of t...This paper presents a new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters （ADC）. The new offset averaging design technique takes full advantage of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging techniques to minimize offset-induced ADC nonlinearities. Circuit analysis allows selection of optimum resistance and capacitance averaging factors to achieve maximum offset reduction in ADC designs. The new averaging method is verified in designing a 4 bit 1 Gs/s flash ADC that is implemented in foundry 0.13 μm CMOS technology.展开更多
Metallic carbon nanotubes （CNTs） have been proposed as a promising alternative to Cu interconnects in future integrated circuits （ICs） for their remarkable conductive, mechanical and thermal properties. Compact eq...Metallic carbon nanotubes （CNTs） have been proposed as a promising alternative to Cu interconnects in future integrated circuits （ICs） for their remarkable conductive, mechanical and thermal properties. Compact equiv alent circuit models for single-walled carbon nanotube （SWCNT） bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional （3D） ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respec tively.展开更多
基金This project was supported by the National"863"High Technology Programof China (2002AA1Z1420)
文摘An improved rate distortion optimization （RDO） algorithm in JPEG2000 is proposed. The proposed algorithm is suitable for integrated circuit （IC） implementation and can reduce 30% computational cost. A hardware architecture which includes control unit, memory, divider, data converter is also given to implement the algorithm. The circuit based on the improved algorithm is tested on FPGAs and integrated in a JPG2000 chip codec core.
基金The National Natural Science Foundation of China(No.61674048,61574052,61474036,61371025)the Project of Anhui Institute of Economics and Management(No.YJKT1417T01)
文摘In order to solve the problem that the testing cost of the three-dimensional integrated circuit(3D IC)is too high,an optimal stacking order scheme is proposed to reduce the mid-bond test cost.A new testing model is built with the general consideration of both the test time for automatic test equipment(ATE)and manufacturing failure factors.An algorithm for testing cost and testing order optimization is proposed,and the minimum testing cost and optimized stacking order can be carried out by taking testing bandwidth and testing power as constraints.To prove the influence of the optimal stacking order on testing costs,two baselines stacked in sequential either in pyramid type or in inverted pyramid type are compared.Based on the benchmarks from ITC 02,experimental results show that for a 5-layer 3D IC,under different constraints,the optimal stacking order can reduce the test costs on average by 13%and 62%,respectively,compared to the pyramid type and inverted pyramid type.Furthermore,with the increase of the stack size,the test costs of the optimized stack order can be decreased.
基金Sponsored by the National Natural Science Foundation of China(No.61271149)
文摘Many 3D IC applications such as MEMS and RF systems require Through-Silicon Via （TSV） with operations for high-speed vertical communication. In this paper, we introduce a novel air-gap coaxial TSV that is suiTab, for such RF applications. Firstly, the detailed fabrication process is described to explain how to acquire such a structure. Then, an Resistor Inductance Conductance Capacitance （RLGC） model is developed to profile the transverse electromagnetic field effect of the proposed air-gap TSV. The model is further verified by a 3D field solver program through the S-parameter comparison. With reference to the numerically simulated results, this analytical model delivers a maximum deviation of less than 6%0, on the conditions of varying diameters, outer to inner radius ratios, and SU-8 central angles, etc. Taking advantages of scalability of the model, a number of air-gap-based TSV designs are simulated, providing 1.6-4.0 times higher bandwidth than the con- ventional coaxial TSVs and leading to an efficient high frequency vertical RF interconnection solution for 3D ICs.
文摘Hardware implementation of Linear Feedback Shift Register (LFSR) plays a great and very important role in communication systems, and in many security devices. In this paper, a design of LFSR with offset mask has been presented, for Direct Sequence Code Division Multiple Access (DS-CDMA) applications. Integrated electronic components have been used. An accessible model facilitating the synthesis on Printed Circuit Boards (PCB) and implementation on Field Programmable Gate Array (FPGA) is offered. In addition, a temporal and spectral analysis of the circuit is performed in order to validate the design. This latter facilitates the generation of pseudo-random codes based on LFSR and their integration into electronic systems.
文摘The novel integrated circuit (IC) temperature sensor presented in this paper works similarly as a two terminal Zener, has breakdown voltage directly proportional to Kelvin temperature at 10 mV/℃, with typical error of less than ±1.0℃ over a temperature range from -50℃ to +125℃. In addition to all the features that conventional IC temperature sensors have, the new device also has very low static power dissipation ( 0.5 mW ) , low output impedance ( less than 1Ω), excellent stability, high reproducibility, and high precision. The sensor's circuit design and layout are discussed in detail. Applications of the sensor include almost any type of temperature sensing over the range of -50℃-+125℃. The low impedance and linear output of the device make interfacing the readout or control circuitry especially easy. Due to the excellent performance and low cost of this sensor, more applications of the sensor over wide temperature range are expected.
文摘With the rapid development of integrated circuit(IC)technology,reusable intelligent property(IP)core design is widely valued by the industry.Based on the in-depth study of the functional characteristics of advanced microcontroller bus architecture(AMBA),a design scheme of IP core is presented,and it is divided into the functional modules,and the structural design of the IP core is completed.The relationship between the internal modules of the IP core is clarified,and the top-down design method is used to build the internal architecture of the IP core.The IP core interface module,register module,baud rate module,transmit module,receive module,and interrupt module are designed in detail by using Verilog language.The simulation results show that the designed IP core supports serial peripheral interface(SPI)protocol,the function coverage of IP core reaches 100%,the maximum working frequency reaches 200 MHz,and the resource occupancy rate is less than 15%.The reusable IP core can support multiple data formats,multiple timing transmission modes,and master/slave operation modes,reducing the resource consumption of hardware circuits and having stronger applicability.
基金the National Natural Science Foundation of China(No.81170507)the Project of Shanghai Committee of Science and Technology(Nos.11140903700 and 12142201200)
文摘This paper proposes a redundant network communication structure for the patient integrated circuit(IC)card payment system in a hospital information system(HIS),compares it with the network structure of normal hospital IC card system,and calculates the reliabilities of the related communications like the RS485communication and the Ethernet communication.The new structure can efectively promote the reliability of the hospital operation and ensure the payment collection when the Ethernet network is broken.The system is applied to a local hospital and the cost-performance rate is satisfactory during the application.
文摘This Special Issue includes five papers from the 2024 IEEE International Conference on Integrated Circuits Technologies and Applications(ICTA),held in Hangzhou,Zhejiang,China,from October 25 to 27,2024.ICTA is an IEEE flagship conference in the field of integrated circuits(ICs)in China,providing a platform for the presentation and exchange of the latest technical achievements and fostering cross-discipline collaboration in IC designs,technologies,and applications within the rapidly evolving technical community.
文摘Monolithic three-dimensional integrated circuits(M3D ICs)have emerged as an innovative solution to overcome the limitations of traditional 2D scaling,offering improved performance,reduced power consumption,and enhanced functionality.Inter-layer vias(ILVs),crucial components of M3D ICs,provide vertical connectivity between layers but are susceptible to manufacturing and operational defects,such as stuck-at faults(SAFs),shorts,and opens,which can compromise system reliability.These challenges necessitate advanced built-in self-test(BIST)methodologies to ensure robust fault detection and localization while minimizing the testing overhead.In this paper,we introduce a novel BIST architecture tailored to efficiently detect ILV defects,particularly in irregularly positioned ILVs,and approximately localize them within clusters,using a walking pattern approach.In the proposed BIST framework,ILVs are grouped according to the probability of fault occurrence,enabling efficient detection of all SAFs and bridging faults(BFs)and most multiple faults within each cluster.This strategy empowers designers to fine-tune fault coverage,localization precision,and test duration to meet specific design requirements.The new BIST method addresses a critical shortcoming of existing solutions by significantly reducing the number of test configurations and overall test time using multiple ILV clusters.The method also enhances efficiency in terms of area and hardware utilization,particularly for larger circuit benchmarks.For instance,in the LU32PEENG benchmark,where ILVs are divided into 64 clusters,the power,area,and hardware overheads are minimized to 0.82%,1.03%,and 1.14%,respectively.
基金The work was partially funded by the Swedish Research Council,by the European 7^(th)Framework Programme under grant agreement FP7-NEMIAC(No.288670)by the European Research Council through the ERC Advanced Grant xMEMs(No.267528)and the ERC Starting Grant M&M’s(No.277879).
文摘The majority of microelectromechanical system(MEMS)devices must be combined with integrated circuits(ICs)for operation in larger electronic systems.While MEMS transducers sense or control physical,optical or chemical quantities,ICs typically provide functionalities related to the signals of these transducers,such as analog-to-digital conversion,amplification,filtering and information processing as well as communication between the MEMS transducer and the outside world.Thus,the vast majority of commercial MEMS products,such as accelerometers,gyroscopes and micro-mirror arrays,are integrated and packaged together with ICs.There are a variety of possible methods of integrating and packaging MEMS and IC components,and the technology of choice strongly depends on the device,the field of application and the commercial requirements.In this review paper,traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed.These include approaches based on the hybrid integration of multiple chips(multi-chip solutions)as well as system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques.These are important technological building blocks for the‘More-Than-Moore’paradigm described in the International Technology Roadmap for Semiconductors.In this paper,the various approaches are categorized in a coherent manner,their merits are discussed,and suitable application areas and implementations are critically investigated.The implications of the different MEMS and IC integration approaches for packaging,testing and final system costs are reviewed.
基金the National Natural Science Foundation of China(61306046,61640421)the Yicheng Elite Project(202371)+3 种基金the Open Project of National Local Joint Engineering Laboratory of RF Integration and Micro-assembly Technology(KFJJ20230101)the National Key Laboratory of Integrated Chips and Systems Project(SLICS-K202316)the Anhui University Research Project(2023AH050481)the Research on Testing Methods and Accuracy of High Frequency Signal Chips(2023AH050500)。
文摘In response to the growing complexity and performance of integrated circuit(IC),there is an urgent need to enhance the testing and stability of IC test equipment.A method was proposed to predict equipment stability using the upper side boundary value of normal distribution.Initially,the K-means clustering algorithm classifies and analyzes sample data.The accuracy of this boundary value is compared under two common confidence levels to select the optimal threshold.A range is then defined to categorize unqualified test data.Through experimental verification,the method achieves the purpose of measuring the stability of qualitative IC equipment through a deterministic threshold value and judging the stability of the equipment by comparing the number of unqualified data with the threshold value,which realizes the goal of long-term operation monitoring and stability analysis of IC test equipment.
基金Supported by the National Natural Science Foundation of China(Nos. 61025021, 60936002, 60729308, 61011130296, and 61020106006)the National Key Projects of Science and Technology of China (No. 2009ZX02023-001-3)
文摘Traditional planar inductors in Radio Frequency （RF） Integrated Circuits （ICs） are plagued by large areas, low quality, and low frequencies. This paper describes a magnetic-based CMOS-compatible RF in- ductor. Magnetic-core inductors with various ferrite-filled structures, spiral structures, and magnetic material permeabilities were simulated to show that this inductor greatly improves the inductance by up to 97% and quality factor by 18.6% over a multi-GHz frequency range. The results indicate that the inductor is a very promising and viable solution to realize miniature, high quality, and high frequency on-chip inductors for high-end RF ICs.
文摘Electrostatic discharge （ESD） induced parasitic effects have serious impacts on performance of radio frequency （RF） integrated circuits （IC）. This paper discusses a comprehensive noise analysis procedure for ESD protection structures and their negative influences on RF ICs. Noise figures （NFs） of commonly used ESD protection structures and their impacts on a single-chip 5.5 GHz low-noise amplifier （LNA） circuit were depicted. A design example in 0.18 μm SiGe BiCMOS was presented. Measurement results confirm that significant noise degradation occurs in the LNA circuit due to ESD-induced noise effects. A practical design procedure for ESD-protected RF ICs is provided for real-world RF IC optimization.
文摘This Special Issue is dedicated to the selected papers from the 2023 IEEE International Conference on Integrated Circuits Technologies and Applications(ICTA),held in Hefei,Anhui,China,from October 27 to 29,2023.ICTA is an IEEE flagship conference in the field of integrated circuits(ICs)in China,providing a platform for the presentation and exchange of the latest technical achievements and fostering cross-discipline collaboration in IC designs,technologies,and applications within the rapidly evolving technical community.
基金National Key Research and Development Program of China,Grant/Award Number:2021YFB2401604The Integration Projects of National Natural Science Foundation of China-State Grid Joint Fund for Smart Grid,Grant/Award Number:U2166602National Natural Science Foundation of China,Grant/Award Number:52241701。
文摘This paper presents a fully customised integrated gate commutated thyristor(IGCT)gate driver monolithic integrated circuit(GDMIC),aiming to address the many shortcomings of traditional IGCT gate driver units composed of discrete components,such as the excessive number of components,low reliability,and complex development processes.The current-source driving characteristics of IGCTs pose significant technical challenges for developing fully customised integrated circuits(IC).The customised requirements of IGCT gate driver chips under various operating conditions are explored regarding functional module division,power sequencing,and chip parameter specifications.However,existing high-side(HS)driver methods exhibit limitations in functional monolithic integration and bipolar complementary metal-oxide-semiconductor compat-ibility.To address these challenges,a novel HS driving topology based on floating linear regulators is proposed.It can achieve synchronised control of multi-channel floating power transistors while supporting 100%duty cycle continuous conduction.The pro-posed GDMIC reduces the three independent HS power supplies to a single multiplexed topology,significantly decreasing circuit complexity.Experimental results validate the feasibility and performance of a 4-inch gate driver prototype based on IGCT current-source management IC,demonstrating significant advantages in reducing the number of components,enhancing device reliability,and simplifying development.The proposed GDMIC offers an innovative development path for future high-power IGCT drivers.
文摘This paper presents a new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters （ADC）. The new offset averaging design technique takes full advantage of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging techniques to minimize offset-induced ADC nonlinearities. Circuit analysis allows selection of optimum resistance and capacitance averaging factors to achieve maximum offset reduction in ADC designs. The new averaging method is verified in designing a 4 bit 1 Gs/s flash ADC that is implemented in foundry 0.13 μm CMOS technology.
基金supported by the National Natural Science Foundation of China(Nos.61234002,61006028,61204044)the National High-Tech Program of China(Nos.2012AA012302,2013AA011203)
文摘Metallic carbon nanotubes （CNTs） have been proposed as a promising alternative to Cu interconnects in future integrated circuits （ICs） for their remarkable conductive, mechanical and thermal properties. Compact equiv alent circuit models for single-walled carbon nanotube （SWCNT） bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional （3D） ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respec tively.
