This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code （CAVLC） decoder with power optimized for the H.264/advanced video coding （AVC） standard. In the proposed design...This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code （CAVLC） decoder with power optimized for the H.264/advanced video coding （AVC） standard. In the proposed design, according to the regularity of the codewords, the first one detector is used to solve the low efficiency and high power dissipation problem within the traditional method of table-searching. Considering the relevance of the data used in the process of runbefore＇s decoding, arithmetic operation is combined with finite state machine （FSM）, which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in the module level and the register level respectively, which reduces 43% of the overall dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at the clock constraint of 100 MHz, the synthesis result shows that the design costs 11 300 gates under a 0.25 μm CMOS technology, which meets the demand of real time decoding in the H.264/AVC standard.展开更多
The study applied a charge-coupled device (CCD) camera to send video signals to 4 DaVinci<sup>TM</sup> development boards (TMS320DM6446) of Texas Instruments (TI) to carry out H.264 Baseline Profile video ...The study applied a charge-coupled device (CCD) camera to send video signals to 4 DaVinci<sup>TM</sup> development boards (TMS320DM6446) of Texas Instruments (TI) to carry out H.264 Baseline Profile video coding. One of the development boards coded in the Variable Bit Rate (VBR) mode, and the other three development boards coded in the Constant Bit Rate (CBR) mode. In addition, the constant rates are 2 Mbps, 1.5 Mbps and 1 Mbps respectively. The H.264 video compression files produced by the boards were analyzed via video analysis software (CodecVisa) in the study. This software can analyze and present the compression data characteristics of the video files under each video frame, i.e., bits/MB, QP, and PSNR. In this research, the characteristics of data of each frame under four different compression conditions were compared. Their differences were calculated and averaged, and the standard deviation was evaluated. It was further connected with the values of quality characteristics and the peak signal to noise ratio (PSNR) of each frame to analyze the relation among the frame quality, the compression rate of CBR, as well as the quantitative granularity. The preliminary conclusion of the study is that the compression behaviors of CBRs in different coding sources are adjusted in a specific proportion in order to cope with the change in frame complexity. The frame will be severely damaged by a critical value during the process of network transmission while the source rate is less than the value of the characteristic.展开更多
基金Project supported by the Applied Materials Shanghai Research and Development Foundation (Grant No.08700741000)the Foundation of Shanghai Municipal Education Commission (Grant No.2006AZ068)
文摘This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code （CAVLC） decoder with power optimized for the H.264/advanced video coding （AVC） standard. In the proposed design, according to the regularity of the codewords, the first one detector is used to solve the low efficiency and high power dissipation problem within the traditional method of table-searching. Considering the relevance of the data used in the process of runbefore＇s decoding, arithmetic operation is combined with finite state machine （FSM）, which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in the module level and the register level respectively, which reduces 43% of the overall dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at the clock constraint of 100 MHz, the synthesis result shows that the design costs 11 300 gates under a 0.25 μm CMOS technology, which meets the demand of real time decoding in the H.264/AVC standard.
文摘The study applied a charge-coupled device (CCD) camera to send video signals to 4 DaVinci<sup>TM</sup> development boards (TMS320DM6446) of Texas Instruments (TI) to carry out H.264 Baseline Profile video coding. One of the development boards coded in the Variable Bit Rate (VBR) mode, and the other three development boards coded in the Constant Bit Rate (CBR) mode. In addition, the constant rates are 2 Mbps, 1.5 Mbps and 1 Mbps respectively. The H.264 video compression files produced by the boards were analyzed via video analysis software (CodecVisa) in the study. This software can analyze and present the compression data characteristics of the video files under each video frame, i.e., bits/MB, QP, and PSNR. In this research, the characteristics of data of each frame under four different compression conditions were compared. Their differences were calculated and averaged, and the standard deviation was evaluated. It was further connected with the values of quality characteristics and the peak signal to noise ratio (PSNR) of each frame to analyze the relation among the frame quality, the compression rate of CBR, as well as the quantitative granularity. The preliminary conclusion of the study is that the compression behaviors of CBRs in different coding sources are adjusted in a specific proportion in order to cope with the change in frame complexity. The frame will be severely damaged by a critical value during the process of network transmission while the source rate is less than the value of the characteristic.
