We present a fractional-order three-dimensional chaotic system, which can generate four-wing chaotic attractor. Dy- namics of the fractional-order system is investigated by numerical simulations. To rigorously verify ...We present a fractional-order three-dimensional chaotic system, which can generate four-wing chaotic attractor. Dy- namics of the fractional-order system is investigated by numerical simulations. To rigorously verify the chaos properties of this system, the existence of horseshoe in the four-wing attractor is presented. Firstly, a Poincar6 section is selected properly, and a first-return Poincar6 map is established. Then, a one-dimensional tensile horseshoe is discovered, which verifies the chaos existence of the system in mathematical view. Finally, the fractional-order chaotic attractor is imple- mented physically with a field-programmable gate array （FPGA） chip, which is useful in further engineering applications of information encryption and secure communications.展开更多
High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the impleme...High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA.展开更多
移动终端通过小区搜索完成与网络的接入工作。为了更快地完成时分长期演进(time division long term evolution,TD-LTE)系统小区搜索过程,与传统数字信号处理(digital signal processing,DSP)串行模式对比,从速度和面积两方面综合考虑,...移动终端通过小区搜索完成与网络的接入工作。为了更快地完成时分长期演进(time division long term evolution,TD-LTE)系统小区搜索过程,与传统数字信号处理(digital signal processing,DSP)串行模式对比,从速度和面积两方面综合考虑,提出一种基于现场可编程门阵列(field programmable gate array,FPGA)的多通道并行小区搜索架构。主要工作集中在小区搜索整体方案设计和FPGA硬件实现上,在算法上对整个小区搜索算法架构进行了改进,同时根据硬件需求,利用以时钟换取速度的思想对FPGA硬件实现架构进行了优化。采用多通道并行高速乘法器进行序列相关检测和动态门限配置的方法,大大缩短了TD-LTE小区搜索的处理时间。并以Altera的EP4SGX230KF40C2芯片作为硬件平台进行了Modelsim功能仿真、板级验证等工作。实验结果表明,该设计方案的处理速度和数据精度均满足TD-LTE系统测试要求,性能远优于传统的DSP架构模式,可以应用到实际工程中。展开更多
为测试可信计算平台的安全性,提出了一种使用现场可编程门阵列(field program gate array,FPGA)搭建监控平台,针对可信平台模块被动工作模式的特点,采用监听、篡改和伪造输入数据等手段对可信平台模块进行攻击,达到攻击可信计算平台的目...为测试可信计算平台的安全性,提出了一种使用现场可编程门阵列(field program gate array,FPGA)搭建监控平台,针对可信平台模块被动工作模式的特点,采用监听、篡改和伪造输入数据等手段对可信平台模块进行攻击,达到攻击可信计算平台的目的.实验结果证明,现有可信计算平台存在中间人攻击的安全隐患.展开更多
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61502340 and 61374169)the Application Base and Frontier Technology Research Project of Tianjin,China(Grant No.15JCYBJC51800)the South African National Research Foundation Incentive Grants(Grant No.81705)
文摘We present a fractional-order three-dimensional chaotic system, which can generate four-wing chaotic attractor. Dy- namics of the fractional-order system is investigated by numerical simulations. To rigorously verify the chaos properties of this system, the existence of horseshoe in the four-wing attractor is presented. Firstly, a Poincar6 section is selected properly, and a first-return Poincar6 map is established. Then, a one-dimensional tensile horseshoe is discovered, which verifies the chaos existence of the system in mathematical view. Finally, the fractional-order chaotic attractor is imple- mented physically with a field-programmable gate array （FPGA） chip, which is useful in further engineering applications of information encryption and secure communications.
基金the National Science Foundation of China(Nos.60934007 and 61074060)the Postdoctoral Science Foundation of China(No.20090460627)+2 种基金the Postdoctoral Scientific Program of Shanghai (No.10R21414600)the Specialized Research Fund for the Doctoral Program of Higher Education (No.20070248004)the China Postdoctoral Science Foundation Special Support(No.201003272)
文摘High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA.
文摘移动终端通过小区搜索完成与网络的接入工作。为了更快地完成时分长期演进(time division long term evolution,TD-LTE)系统小区搜索过程,与传统数字信号处理(digital signal processing,DSP)串行模式对比,从速度和面积两方面综合考虑,提出一种基于现场可编程门阵列(field programmable gate array,FPGA)的多通道并行小区搜索架构。主要工作集中在小区搜索整体方案设计和FPGA硬件实现上,在算法上对整个小区搜索算法架构进行了改进,同时根据硬件需求,利用以时钟换取速度的思想对FPGA硬件实现架构进行了优化。采用多通道并行高速乘法器进行序列相关检测和动态门限配置的方法,大大缩短了TD-LTE小区搜索的处理时间。并以Altera的EP4SGX230KF40C2芯片作为硬件平台进行了Modelsim功能仿真、板级验证等工作。实验结果表明,该设计方案的处理速度和数据精度均满足TD-LTE系统测试要求,性能远优于传统的DSP架构模式,可以应用到实际工程中。
文摘为测试可信计算平台的安全性,提出了一种使用现场可编程门阵列(field program gate array,FPGA)搭建监控平台,针对可信平台模块被动工作模式的特点,采用监听、篡改和伪造输入数据等手段对可信平台模块进行攻击,达到攻击可信计算平台的目的.实验结果证明,现有可信计算平台存在中间人攻击的安全隐患.
