High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the impleme...High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA.展开更多
This paper will provide some insights on the application of Field Programmable Gate Array (FPGA) in process tomography. The focus of this paper will be to investigate the performance of the technology with respect to ...This paper will provide some insights on the application of Field Programmable Gate Array (FPGA) in process tomography. The focus of this paper will be to investigate the performance of the technology with respect to various tomography systems and comparison to other similar technologies including the Application Specific Integrated Circuit (ASIC), Graphics Processing Unit (GPU) and the microcontroller. Fundamentally, the FPGA is primarily used in the Data Acquisition System (DAQ) due to its better performance and better trade-off as compared to competitor technologies. However, the drawback of using FPGA is that it is relatively more expensive.展开更多
Real-time digital audio processing plays a crucial role in modern electronic systems,such as mobile devices,communication platforms,and multimedia applications.However,ensuring high-performance,low-latency processing ...Real-time digital audio processing plays a crucial role in modern electronic systems,such as mobile devices,communication platforms,and multimedia applications.However,ensuring high-performance,low-latency processing under hardware constraints remains a significant challenge,particularly when integrating audio codec chips with FPGA platforms.This paper presents the design and implementation of a real-time digital audio processing system using field-programmable gate array(FPGA)technology and the WM8731 audio codec.Firstly,a robust Inter-Integrated Circuit(I2C)interface is developed to configure the WM8731 codec,ensuring accurate initialization and stable operation.Secondly,a serial-to-parallel adaptor(s2p_adaptor)is designed to convert inter-IC sound(I2S)serial audio data into parallel format for digital processing,synchronized with bit and frame clocks.Finally,an 8-tap finite impulse response(FIR)filter is implemented using very high speed integrated circuit(VHSIC)hardware description language(VHDL)to enhance audio quality by suppressing high-frequency noise.All modules are synthesized in Quartus II and verified through ModelSim simulations and practical testing on an Altera DE1 development board.Timing diagrams based on the WM8731 datasheet and internal clock signals ensure precise synchronization.Experimental results demonstrate the effectiveness of the system,while final analysis highlights areas for further optimization and future improvements.Beyond audio applications,the proposed architecture is also adaptable to other real-time signal processing tasks,such as biomedical monitoring,radar front-end filtering,and image preprocessing.This extensibility enhances the system’s relevance in broader embedded and communication contexts.展开更多
To enhance the real-time performance of image processing,effectively reduce video transmission bandwidth and storage space,and improve transmission efficiency,a real-time image processing system was designed using a F...To enhance the real-time performance of image processing,effectively reduce video transmission bandwidth and storage space,and improve transmission efficiency,a real-time image processing system was designed using a Field Programmable Gate Array(FPGA).The system is mainly divided into image acquisition,image processing,and image display subsystems.Images are captured using a camera module and transmitted to the image processing module for processing,and finally displayed via an HDMI monitor.Measurements indicate that the system has strong real-time performance,low power consumption,and high portability,making it valuable in fields such as surveillance and security,medical imaging,and industrial automation.展开更多
In order to eliminate the drawbacks of conventional force feedback gloves, a new type of master fin- ger has been developed. By utilizing three ＂four-bar mechanism joint＂ in series and wire coupling mecha- nism, the...In order to eliminate the drawbacks of conventional force feedback gloves, a new type of master fin- ger has been developed. By utilizing three ＂four-bar mechanism joint＂ in series and wire coupling mecha- nism, the master finger transmission ratio is kept exactly 1：1.4：1 in the whole movement range and it can make active motions in both extension and flexion directions. Additionally, to assure faster data transmission and near zero delay in the master-slave operation, a digital signal processing/field programmable gate array （DSP/FPGA-FPGA） structure with 200μs cycle time is designed. The operating modes of the master finger can be contact or non-contact, which depends on the motion states of a slave finger, free motion or constrained motion. The position control employed in non-contact mode ensures unconstrained motion and the force control adopted in contact mode guarantees natural contact sensation. To evaluate the performances of the master finger, an experiment between the master finger and a DLR/HTT dexterous finger is conducted. The results demonstrate that this new type master finger can augment telepresence.展开更多
The wide acceptance and data deluge in medical imaging processing require faster and more efficient systems to be built.Due to the advances in heterogeneous architectures recently,there has been a resurgence in the fi...The wide acceptance and data deluge in medical imaging processing require faster and more efficient systems to be built.Due to the advances in heterogeneous architectures recently,there has been a resurgence in the first research aimed at FPGA-based as well as GPGPU-based accelerator design.This paper quantitatively analyzes the workload,computational intensity and memory performance of a single-particle 3D reconstruction application,called EMAN,and parallelizes it on CUDA GPGPU architectures and decouples the memory operations from the computing flow and orchestrates the thread-data mapping to reduce the overhead of off-chip memory operations.Then it exploits the trend towards FPGA-based accelerator design,which is achieved by offloading computingintensive kernels to dedicated hardware modules.Furthermore,a customized memory subsystem is also designed to facilitate the decoupling and optimization of computing dominated data access patterns.This paper evaluates the proposed accelerator design strategies by comparing it with a parallelized program on a 4-cores CPU.The CUDA version on a GTX480 shows a speedup of about 6 times.The performance of the stream architecture implemented on a Xilinx Virtex LX330 FPGA is justified by the reported speedup of 2.54 times.Meanwhile,measured in terms of power efficiency,the FPGA-based accelerator outperforms a 4-cores CPU and a GTX480 by 7.3 times and 3.4 times,respectively.展开更多
基金the National Science Foundation of China(Nos.60934007 and 61074060)the Postdoctoral Science Foundation of China(No.20090460627)+2 种基金the Postdoctoral Scientific Program of Shanghai (No.10R21414600)the Specialized Research Fund for the Doctoral Program of Higher Education (No.20070248004)the China Postdoctoral Science Foundation Special Support(No.201003272)
文摘High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA.
文摘This paper will provide some insights on the application of Field Programmable Gate Array (FPGA) in process tomography. The focus of this paper will be to investigate the performance of the technology with respect to various tomography systems and comparison to other similar technologies including the Application Specific Integrated Circuit (ASIC), Graphics Processing Unit (GPU) and the microcontroller. Fundamentally, the FPGA is primarily used in the Data Acquisition System (DAQ) due to its better performance and better trade-off as compared to competitor technologies. However, the drawback of using FPGA is that it is relatively more expensive.
基金supported by the Major Scientific Instruments and Equipments Development Project of the National Natural Science Foundation of China(No.62427809)the National Natural Science Foundation of China(Nos.62372248,62302235,and 62402241)+2 种基金the Key Program of Natural Science Foundation of Jiangsu(Nos.BK20243053 and 24KJA520006)the Natural Science Foundation of Jiangsu Province(No.BK20230352)the Postgraduate Research&Practice Innovation Program of Jiangsu Province(No.SJCX240316).
文摘Real-time digital audio processing plays a crucial role in modern electronic systems,such as mobile devices,communication platforms,and multimedia applications.However,ensuring high-performance,low-latency processing under hardware constraints remains a significant challenge,particularly when integrating audio codec chips with FPGA platforms.This paper presents the design and implementation of a real-time digital audio processing system using field-programmable gate array(FPGA)technology and the WM8731 audio codec.Firstly,a robust Inter-Integrated Circuit(I2C)interface is developed to configure the WM8731 codec,ensuring accurate initialization and stable operation.Secondly,a serial-to-parallel adaptor(s2p_adaptor)is designed to convert inter-IC sound(I2S)serial audio data into parallel format for digital processing,synchronized with bit and frame clocks.Finally,an 8-tap finite impulse response(FIR)filter is implemented using very high speed integrated circuit(VHSIC)hardware description language(VHDL)to enhance audio quality by suppressing high-frequency noise.All modules are synthesized in Quartus II and verified through ModelSim simulations and practical testing on an Altera DE1 development board.Timing diagrams based on the WM8731 datasheet and internal clock signals ensure precise synchronization.Experimental results demonstrate the effectiveness of the system,while final analysis highlights areas for further optimization and future improvements.Beyond audio applications,the proposed architecture is also adaptable to other real-time signal processing tasks,such as biomedical monitoring,radar front-end filtering,and image preprocessing.This extensibility enhances the system’s relevance in broader embedded and communication contexts.
文摘To enhance the real-time performance of image processing,effectively reduce video transmission bandwidth and storage space,and improve transmission efficiency,a real-time image processing system was designed using a Field Programmable Gate Array(FPGA).The system is mainly divided into image acquisition,image processing,and image display subsystems.Images are captured using a camera module and transmitted to the image processing module for processing,and finally displayed via an HDMI monitor.Measurements indicate that the system has strong real-time performance,low power consumption,and high portability,making it valuable in fields such as surveillance and security,medical imaging,and industrial automation.
文摘In order to eliminate the drawbacks of conventional force feedback gloves, a new type of master fin- ger has been developed. By utilizing three ＂four-bar mechanism joint＂ in series and wire coupling mecha- nism, the master finger transmission ratio is kept exactly 1：1.4：1 in the whole movement range and it can make active motions in both extension and flexion directions. Additionally, to assure faster data transmission and near zero delay in the master-slave operation, a digital signal processing/field programmable gate array （DSP/FPGA-FPGA） structure with 200μs cycle time is designed. The operating modes of the master finger can be contact or non-contact, which depends on the motion states of a slave finger, free motion or constrained motion. The position control employed in non-contact mode ensures unconstrained motion and the force control adopted in contact mode guarantees natural contact sensation. To evaluate the performances of the master finger, an experiment between the master finger and a DLR/HTT dexterous finger is conducted. The results demonstrate that this new type master finger can augment telepresence.
基金Supported by the National Basic Research Program of China(No.2012CB316502)the National High Technology Research and DevelopmentProgram of China(No.2009AA01A129)the National Natural Science Foundation of China(No.60921002)
文摘The wide acceptance and data deluge in medical imaging processing require faster and more efficient systems to be built.Due to the advances in heterogeneous architectures recently,there has been a resurgence in the first research aimed at FPGA-based as well as GPGPU-based accelerator design.This paper quantitatively analyzes the workload,computational intensity and memory performance of a single-particle 3D reconstruction application,called EMAN,and parallelizes it on CUDA GPGPU architectures and decouples the memory operations from the computing flow and orchestrates the thread-data mapping to reduce the overhead of off-chip memory operations.Then it exploits the trend towards FPGA-based accelerator design,which is achieved by offloading computingintensive kernels to dedicated hardware modules.Furthermore,a customized memory subsystem is also designed to facilitate the decoupling and optimization of computing dominated data access patterns.This paper evaluates the proposed accelerator design strategies by comparing it with a parallelized program on a 4-cores CPU.The CUDA version on a GTX480 shows a speedup of about 6 times.The performance of the stream architecture implemented on a Xilinx Virtex LX330 FPGA is justified by the reported speedup of 2.54 times.Meanwhile,measured in terms of power efficiency,the FPGA-based accelerator outperforms a 4-cores CPU and a GTX480 by 7.3 times and 3.4 times,respectively.
