The earthquake early warning system is an effective means of disaster reduction to reduce losses caused by earthquakes,it can release earthquake warning information to the public before destructive seismic waves reach...The earthquake early warning system is an effective means of disaster reduction to reduce losses caused by earthquakes,it can release earthquake warning information to the public before destructive seismic waves reach the warning target area,and carry out automatic disposal of lifeline engineering facilities.Through the construction of the National Earthquake Intensity Rapid Reporting and Early Warning Project,an earthquake early warning network consisting of over 1900 monitoring stations has been established in the Beijing-Tianjin-Hebei Urban Agglomeration.The early warning system has achieved second level earthquake warning and minute level intensity rapid reporting.The implementation of these functions relies on the system's ability to timely,accurately,and reliably identify seismic waves.But with the development of social economy,the background noise of earthquake observation environment is becoming increasingly complex,which brings certain challenges to earthquake wave recognition,some interference events have the risk of triggering the earthquake warning system incorrectly.Therefore,this article focuses on seismic wave recognition in complex noise environments and proposes a seismic wave detection method based on triangulation to enhance the antiinterference ability and recognition accuracy of early warning systems.展开更多
This work presents the design of a novel static-triggered power-rail electrostatic discharge(ESD)clamp circuit. The superior transient-noise immunity of the static ESD detection mechanism over the transient one is fir...This work presents the design of a novel static-triggered power-rail electrostatic discharge(ESD)clamp circuit. The superior transient-noise immunity of the static ESD detection mechanism over the transient one is firstly discussed. Based on the discussion, a novel power-rail ESD clamp circuit utilizing the static ESD detection mechanism is proposed. By skillfully incorporating a thyristor delay stage into the trigger circuit(TC), the proposed circuit achieves the best ESD-conduction behavior while consuming the lowest leakage current(Ileak) at the normal bias voltage among all investigated circuits in this work. In addition, the proposed circuit achieves an excellent false-triggering immunity against fast power-up pulses. All investigated circuits are fabricated in a 65-nm CMOS process. Performance superiorities of the proposed circuit are fully verified by both simulation and test results. Moreover, the proposed circuit offers an efficient on-chip ESD protection scheme considering the worst discharge case in the utilized process.展开更多
A MOSFET-based electrostatic discharge （ESD） power clamp circuit with only a 10 ns RC time constant for a 0.18-μm process is proposed. A diode-connected NMOSFET is used to maintain a long delay time and save area. ...A MOSFET-based electrostatic discharge （ESD） power clamp circuit with only a 10 ns RC time constant for a 0.18-μm process is proposed. A diode-connected NMOSFET is used to maintain a long delay time and save area. The special structure overcomes other shortcomings in this clamp circuit. Under fast power-up events, the gate voltage of the clamp MOSFET does not rise as quickly as under ESD events, the special structure can keep the clamp MOSFET thoroughly off. Under a falsely triggered event, the special structure can turn off the clamp MOSFET in a short time. The clamp circuit can also reject the power supply noise effectively. Simulation results show that the clamp circuit avoids fast false triggering events such as a 30 ns/1.8 V power-up, maintains a 1.2 μs delay time and a 2.14 μs turn-off time, and reduces to about 70% of the RC time constant. It is believed that the proposed clamp circuit can be widely used in high-speed integrated circuits.展开更多
基金supported by the Spark Program of Earthquake Science and Technology(No.XH23003C)。
文摘The earthquake early warning system is an effective means of disaster reduction to reduce losses caused by earthquakes,it can release earthquake warning information to the public before destructive seismic waves reach the warning target area,and carry out automatic disposal of lifeline engineering facilities.Through the construction of the National Earthquake Intensity Rapid Reporting and Early Warning Project,an earthquake early warning network consisting of over 1900 monitoring stations has been established in the Beijing-Tianjin-Hebei Urban Agglomeration.The early warning system has achieved second level earthquake warning and minute level intensity rapid reporting.The implementation of these functions relies on the system's ability to timely,accurately,and reliably identify seismic waves.But with the development of social economy,the background noise of earthquake observation environment is becoming increasingly complex,which brings certain challenges to earthquake wave recognition,some interference events have the risk of triggering the earthquake warning system incorrectly.Therefore,this article focuses on seismic wave recognition in complex noise environments and proposes a seismic wave detection method based on triangulation to enhance the antiinterference ability and recognition accuracy of early warning systems.
基金supported by National Science and Technology Major Project of China(Grant No.2013ZX02303002)
文摘This work presents the design of a novel static-triggered power-rail electrostatic discharge(ESD)clamp circuit. The superior transient-noise immunity of the static ESD detection mechanism over the transient one is firstly discussed. Based on the discussion, a novel power-rail ESD clamp circuit utilizing the static ESD detection mechanism is proposed. By skillfully incorporating a thyristor delay stage into the trigger circuit(TC), the proposed circuit achieves the best ESD-conduction behavior while consuming the lowest leakage current(Ileak) at the normal bias voltage among all investigated circuits in this work. In addition, the proposed circuit achieves an excellent false-triggering immunity against fast power-up pulses. All investigated circuits are fabricated in a 65-nm CMOS process. Performance superiorities of the proposed circuit are fully verified by both simulation and test results. Moreover, the proposed circuit offers an efficient on-chip ESD protection scheme considering the worst discharge case in the utilized process.
基金supported by the National Natural Science Foundation of China(Nos.60976068,60936005)the Cultivation Fund of the Key Scientific and Technical Innovation Project,Ministry of Education of China(No.708083)
文摘A MOSFET-based electrostatic discharge （ESD） power clamp circuit with only a 10 ns RC time constant for a 0.18-μm process is proposed. A diode-connected NMOSFET is used to maintain a long delay time and save area. The special structure overcomes other shortcomings in this clamp circuit. Under fast power-up events, the gate voltage of the clamp MOSFET does not rise as quickly as under ESD events, the special structure can keep the clamp MOSFET thoroughly off. Under a falsely triggered event, the special structure can turn off the clamp MOSFET in a short time. The clamp circuit can also reject the power supply noise effectively. Simulation results show that the clamp circuit avoids fast false triggering events such as a 30 ns/1.8 V power-up, maintains a 1.2 μs delay time and a 2.14 μs turn-off time, and reduces to about 70% of the RC time constant. It is believed that the proposed clamp circuit can be widely used in high-speed integrated circuits.
