针对在现场可编程门阵列(Field Programmable Gate Array,FPGA)上实现基于极化敏感阵列的多重信号分类(Multiple Signal Classification,MUSIC)算法进行二维波达方向(Direction of Arrival,DOA)和二维极化参数联合估计时,硬件资源占用...针对在现场可编程门阵列(Field Programmable Gate Array,FPGA)上实现基于极化敏感阵列的多重信号分类(Multiple Signal Classification,MUSIC)算法进行二维波达方向(Direction of Arrival,DOA)和二维极化参数联合估计时,硬件资源占用大、运行时间长的问题,提出了一种基于极化MUSIC算法的四维参数联合估计FPGA实现架构。该架构包括信号协方差矩阵计算模块、Jacobi旋转模块、噪声子空间提取模块、两级空间谱搜索模块和极化参数计算模块。Jacobi旋转模块被拆分为多个可复用模块,并采用查找表模块生成旋转矩阵。一级空间谱搜索模块通过二维DOA搜索初步确定信源的角度信息。二级空间谱搜索模块根据一级搜索的角度结果确定二级搜索区域各点的极化信息,并计算该区域的四维空间谱,区域内最小值对应的四维参数信息即为最终估计的信源方向角、俯仰角、极化辅助角和极化相位角。仿真结果表明,与传统极化MUSIC算法的四维搜索算法相比,该架构避免了大量四维空间谱计算,同时保证了四维参数估计的精度,显著减少了运行时间和硬件资源消耗。展开更多
在核脉冲信号处理中,梯形成形算法发挥着至关重要的作用,传统梯形成形算法常面临手动参数调节复杂、噪声敏感及实时性不足等问题。针对上述问题,设计了一种基于最小均方(Least Mean Squares,LMS)的双通道自适应梯形成形滤波算法,通过自...在核脉冲信号处理中,梯形成形算法发挥着至关重要的作用,传统梯形成形算法常面临手动参数调节复杂、噪声敏感及实时性不足等问题。针对上述问题,设计了一种基于最小均方(Least Mean Squares,LMS)的双通道自适应梯形成形滤波算法,通过自适应调整梯形参数实时修正成形过程中的偏差,避免了手动调节的复杂性。首先,使用MATLAB进行算法仿真验证,随后通过Verilog语言实现并部署至FPGA平台进行实测,实现了算法的高效验证和落地。该算法不仅解决了现有方法的不足,优化了梯形成形滤波算法,还对双指数脉冲信号进行了探讨,实现了复杂信号的梯形成形参数自适应调节。实验结果表明,经LMS自适应算法控制的梯形成形滤波算法,收敛时间缩减到15~25μs,动态适应范围τ提升到0.3~50μs,具有良好的噪声抑制效果以及滤波成形能力。本文研究为核脉冲信号探测提供了一种有效的方法,对相关应用具有重要的参考价值。展开更多
Genetic Algorithm (GA) is a biologically inspired technique and widely used to solve numerous combinational optimization problems. It works on a population of individuals, not just one single solution. As a result, it...Genetic Algorithm (GA) is a biologically inspired technique and widely used to solve numerous combinational optimization problems. It works on a population of individuals, not just one single solution. As a result, it avoids converging to the local optimum. However, it takes too much CPU time in the late process of GA. On the other hand, in the late process Simulated Annealing (SA) converges faster than GA but it is easily trapped to local optimum. In this letter, a useful method that unifies GA and SA is introduced, which utilizes the advantage of the global search ability of GA and fast convergence of SA. The experimental results show that the proposed algorithm outperforms GA in terms of CPU time without degradation of performance. It also achieves highly comparable placement cost compared to the state-of-the-art results obtained by Versatile Place and Route (VPR) Tool.展开更多
Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-F...Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-FPGA SEU capability, the registers of the circuit netlist are tripled and divided into three categories in this study. By the packing algorithm, the registers of triple modular redundancy are loaded into different configurable logic block. At the same time, the packing algorithm considers the effect of large fan-out nets. The experimental results show that the algorithm successfully realize the packing of the register of Triple Modular Redundancy(TMR). Comparing with Timing Versatile PACKing(TVPACK), the algorithm in this study is able to obtain a 11% reduction of the number of the nets in critical path, and a 12% reduction of the time delay in critical path on average when TMR is not considered. Especially, some critical path delay of circuit can be improved about 33%.展开更多
文摘针对在现场可编程门阵列(Field Programmable Gate Array,FPGA)上实现基于极化敏感阵列的多重信号分类(Multiple Signal Classification,MUSIC)算法进行二维波达方向(Direction of Arrival,DOA)和二维极化参数联合估计时,硬件资源占用大、运行时间长的问题,提出了一种基于极化MUSIC算法的四维参数联合估计FPGA实现架构。该架构包括信号协方差矩阵计算模块、Jacobi旋转模块、噪声子空间提取模块、两级空间谱搜索模块和极化参数计算模块。Jacobi旋转模块被拆分为多个可复用模块,并采用查找表模块生成旋转矩阵。一级空间谱搜索模块通过二维DOA搜索初步确定信源的角度信息。二级空间谱搜索模块根据一级搜索的角度结果确定二级搜索区域各点的极化信息,并计算该区域的四维空间谱,区域内最小值对应的四维参数信息即为最终估计的信源方向角、俯仰角、极化辅助角和极化相位角。仿真结果表明,与传统极化MUSIC算法的四维搜索算法相比,该架构避免了大量四维空间谱计算,同时保证了四维参数估计的精度,显著减少了运行时间和硬件资源消耗。
文摘在核脉冲信号处理中,梯形成形算法发挥着至关重要的作用,传统梯形成形算法常面临手动参数调节复杂、噪声敏感及实时性不足等问题。针对上述问题,设计了一种基于最小均方(Least Mean Squares,LMS)的双通道自适应梯形成形滤波算法,通过自适应调整梯形参数实时修正成形过程中的偏差,避免了手动调节的复杂性。首先,使用MATLAB进行算法仿真验证,随后通过Verilog语言实现并部署至FPGA平台进行实测,实现了算法的高效验证和落地。该算法不仅解决了现有方法的不足,优化了梯形成形滤波算法,还对双指数脉冲信号进行了探讨,实现了复杂信号的梯形成形参数自适应调节。实验结果表明,经LMS自适应算法控制的梯形成形滤波算法,收敛时间缩减到15~25μs,动态适应范围τ提升到0.3~50μs,具有良好的噪声抑制效果以及滤波成形能力。本文研究为核脉冲信号探测提供了一种有效的方法,对相关应用具有重要的参考价值。
基金Supported by School of Engineering, Napier University, United Kingdom, and partially supported by the National Natural Science Foundation of China (No.60273093).
文摘Genetic Algorithm (GA) is a biologically inspired technique and widely used to solve numerous combinational optimization problems. It works on a population of individuals, not just one single solution. As a result, it avoids converging to the local optimum. However, it takes too much CPU time in the late process of GA. On the other hand, in the late process Simulated Annealing (SA) converges faster than GA but it is easily trapped to local optimum. In this letter, a useful method that unifies GA and SA is introduced, which utilizes the advantage of the global search ability of GA and fast convergence of SA. The experimental results show that the proposed algorithm outperforms GA in terms of CPU time without degradation of performance. It also achieves highly comparable placement cost compared to the state-of-the-art results obtained by Versatile Place and Route (VPR) Tool.
基金Supported by the National Natural Science Foundation of China(No.61106033)
文摘Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-FPGA SEU capability, the registers of the circuit netlist are tripled and divided into three categories in this study. By the packing algorithm, the registers of triple modular redundancy are loaded into different configurable logic block. At the same time, the packing algorithm considers the effect of large fan-out nets. The experimental results show that the algorithm successfully realize the packing of the register of Triple Modular Redundancy(TMR). Comparing with Timing Versatile PACKing(TVPACK), the algorithm in this study is able to obtain a 11% reduction of the number of the nets in critical path, and a 12% reduction of the time delay in critical path on average when TMR is not considered. Especially, some critical path delay of circuit can be improved about 33%.
