本文主要研究高性能FPGA可编程逻辑单元中分布式RAM和移位寄存器两种时序功能的设计实现方法.运用静态Latch实现分布式RAM的写入同步,以降低对时序控制电路的要求;为克服电荷共享问题,提出通过隔断存储单元之间通路的方法实现移位寄存器...本文主要研究高性能FPGA可编程逻辑单元中分布式RAM和移位寄存器两种时序功能的设计实现方法.运用静态Latch实现分布式RAM的写入同步,以降低对时序控制电路的要求;为克服电荷共享问题,提出通过隔断存储单元之间通路的方法实现移位寄存器.以含两个四输入LUT(Look Up Table)的多功能可编程逻辑单元为例,详细说明电路的设计思路以及实现方法.研究表明,本文提出的方法可以简化对时序控制电路的设计要求,克服电荷共享问题,减少芯片面积.展开更多
A new LUT and carry structure embedded in the configurable logic block of an FPGA is proposed. The LUT is designed to support both 4-input and 5-input structures, which can be configured by users according to their ne...A new LUT and carry structure embedded in the configurable logic block of an FPGA is proposed. The LUT is designed to support both 4-input and 5-input structures, which can be configured by users according to their needs without increasing interconnect resources. We also develop a new carry chain structure with an optimized critical path. Finally a newly designed configurable scan-chain is inserted. The circuit is fabricated in 0.13μm 1P8M 1.2/2.5/3.3 V logic CMOS process. The test results show a correct function of 4/5-input LUT and scan- chain, and a speedup in carry performance of nearly 3 times over current architecture in the same technology at the cost of an increase in total area of about 72.5%. Our results also show that the logic utilization of this work is better than that of a Virtex lI/Virtex 4/Virtex 5/Virtex 6/Virtex 7 FPGA when implemented using only 4-LUT and better than that of a Virtex lI/Virtex 4 FPGA when implemented using only 5-LUT.展开更多
文摘本文主要研究高性能FPGA可编程逻辑单元中分布式RAM和移位寄存器两种时序功能的设计实现方法.运用静态Latch实现分布式RAM的写入同步,以降低对时序控制电路的要求;为克服电荷共享问题,提出通过隔断存储单元之间通路的方法实现移位寄存器.以含两个四输入LUT(Look Up Table)的多功能可编程逻辑单元为例,详细说明电路的设计思路以及实现方法.研究表明,本文提出的方法可以简化对时序控制电路的设计要求,克服电荷共享问题,减少芯片面积.
基金supported by the National High Technology Research and Development Thematic Program of China(No.2012AA012001)
文摘A new LUT and carry structure embedded in the configurable logic block of an FPGA is proposed. The LUT is designed to support both 4-input and 5-input structures, which can be configured by users according to their needs without increasing interconnect resources. We also develop a new carry chain structure with an optimized critical path. Finally a newly designed configurable scan-chain is inserted. The circuit is fabricated in 0.13μm 1P8M 1.2/2.5/3.3 V logic CMOS process. The test results show a correct function of 4/5-input LUT and scan- chain, and a speedup in carry performance of nearly 3 times over current architecture in the same technology at the cost of an increase in total area of about 72.5%. Our results also show that the logic utilization of this work is better than that of a Virtex lI/Virtex 4/Virtex 5/Virtex 6/Virtex 7 FPGA when implemented using only 4-LUT and better than that of a Virtex lI/Virtex 4 FPGA when implemented using only 5-LUT.
