SPHINCS+is a hash-based digital signature scheme that has been selected for post-quantum cryptography(PQC)standardization announced by the U.S.National Institute of Standards and Technology(NIST)in 2022.Although SPHIN...SPHINCS+is a hash-based digital signature scheme that has been selected for post-quantum cryptography(PQC)standardization announced by the U.S.National Institute of Standards and Technology(NIST)in 2022.Although SPHINCS+offers significant security against quantum attacks,its relatively slow computation times present a major obstacle to its practical deployment.To address this challenge,improving the computational efficiency of SPHINCS+becomes a critical task.The cryptographic operations in SPHINCS+rely on tweakable hash functions,with various hash algorithms available for selection.Among these,SHA-3 stands out as a widely adopted and NIST-standardized hash function,making it a preferred choice for implementation in SPHINCS+.In this work,we propose a dedicated coprocessor that integrates a SHA-3 accelerator along with its associated peripheral structure.This coprocessor is designed to extend the RISC-V instruction set by incorporating seven custom instructions,enabling efficient software-hardware co-acceleration.Furthermore,we investigate the parallelizable components within SPHINCS+,specifically the FORS and WOTS+Algorithms,to identify means for optimization.By leveraging thread-level parallelism through multi-core programming,we achieve significant improvements in performance.To validate the design,synthesis is performed using TSMC 28-nm CMOS technology at 800 MHz.Compared to the benchmark results from the ARM Cortex-M4 processor,our approach achieves an impressive 23.1×speedup in the overall single-core performance of SPHINCS+,with an additional 3.4×speedup for the verification process by utilizing multi-core acceleration.展开更多
This paper illustrates the importance of the configuration of function units and the change of an application’s critical path when using instruction set extension （ISE） with multi-issue architectures. This paper al...This paper illustrates the importance of the configuration of function units and the change of an application’s critical path when using instruction set extension （ISE） with multi-issue architectures. This paper also presents an automatic identification approach for customized instruction without input/output number constraints for multi-issue architectures. The approach identifies customized instructions using multiple attribute decision-making based on the analysis of several attributes for each candidate node. Tests indicate that the approach achieves higher speedup ratios than previous approaches, as well as less area cost. In addition, this approach provides designers with multiple candidate designs.展开更多
基金supported by the National Natural Science Foundation of China under Grant 62234008Grant 61934002.
文摘SPHINCS+is a hash-based digital signature scheme that has been selected for post-quantum cryptography(PQC)standardization announced by the U.S.National Institute of Standards and Technology(NIST)in 2022.Although SPHINCS+offers significant security against quantum attacks,its relatively slow computation times present a major obstacle to its practical deployment.To address this challenge,improving the computational efficiency of SPHINCS+becomes a critical task.The cryptographic operations in SPHINCS+rely on tweakable hash functions,with various hash algorithms available for selection.Among these,SHA-3 stands out as a widely adopted and NIST-standardized hash function,making it a preferred choice for implementation in SPHINCS+.In this work,we propose a dedicated coprocessor that integrates a SHA-3 accelerator along with its associated peripheral structure.This coprocessor is designed to extend the RISC-V instruction set by incorporating seven custom instructions,enabling efficient software-hardware co-acceleration.Furthermore,we investigate the parallelizable components within SPHINCS+,specifically the FORS and WOTS+Algorithms,to identify means for optimization.By leveraging thread-level parallelism through multi-core programming,we achieve significant improvements in performance.To validate the design,synthesis is performed using TSMC 28-nm CMOS technology at 800 MHz.Compared to the benchmark results from the ARM Cortex-M4 processor,our approach achieves an impressive 23.1×speedup in the overall single-core performance of SPHINCS+,with an additional 3.4×speedup for the verification process by utilizing multi-core acceleration.
基金Supported by the Basic Research Fund of Tsinghua University
文摘This paper illustrates the importance of the configuration of function units and the change of an application’s critical path when using instruction set extension （ISE） with multi-issue architectures. This paper also presents an automatic identification approach for customized instruction without input/output number constraints for multi-issue architectures. The approach identifies customized instructions using multiple attribute decision-making based on the analysis of several attributes for each candidate node. Tests indicate that the approach achieves higher speedup ratios than previous approaches, as well as less area cost. In addition, this approach provides designers with multiple candidate designs.
