Nowadays more and more attraction is drawn by the event based implicit invocation one of useful architectural patterns, because of its loose coupling between components in the architecture and reactive integration...Nowadays more and more attraction is drawn by the event based implicit invocation one of useful architectural patterns, because of its loose coupling between components in the architecture and reactive integration in software systems. Analyzing object oriented interaction with objects, this paper, based upon the principle of software architecture, presents an approach on event based object model with Ada exception handler. Consequently it is possible for us to improve, with adding specific architectural patterns, traditional programming languages into architectural description languages.展开更多
Abstract To improve the reliability of spaceborne electronic systems, a fault-tolerant strategy of selective triple modular redundancy （STMR） based on multi-objective optimization and evolvable hardware （EHW） agai...Abstract To improve the reliability of spaceborne electronic systems, a fault-tolerant strategy of selective triple modular redundancy （STMR） based on multi-objective optimization and evolvable hardware （EHW） against single-event upsets （SEUs） for circuits implemented on field pro- grammable gate arrays （FPGAs） based on static random access memory （SRAM） is presented in this paper. Various topologies of circuit with the same functionality are evolved using EHW firstly. Then the SEU-sensitive gates of each circuit are identified using signal probabilities of all the lines in it, and each circuit is hardened against SEUs by selectively applying triple modular redundancy （TMR） to these SEU-sensitive gates. Afterward, each circuit hardened has been evaluated by SEU Simulation, and the multi-objective optimization technology is introduced to optimize the area overhead and the number of functional errors of all the circuits, The proposed fault-tolerant strategy is tested on four circuits from microelectronics center of North Carolina （MCNC） benchmark suite. The experimental results show that it can generate innovative trade-off solutions to compromise between hardware resource consumption and system reliability. The maximum savings in the area overhead of the STMR circuit over the full TMR design is 58% with the same SEU immunity.展开更多
基金Supported by National Natural Science Foundation of China(6 97730 41)
文摘Nowadays more and more attraction is drawn by the event based implicit invocation one of useful architectural patterns, because of its loose coupling between components in the architecture and reactive integration in software systems. Analyzing object oriented interaction with objects, this paper, based upon the principle of software architecture, presents an approach on event based object model with Ada exception handler. Consequently it is possible for us to improve, with adding specific architectural patterns, traditional programming languages into architectural description languages.
基金supported by National Natural Science Foundation of China(No.61402226)supported by the Fundamental Research Funds for the Central Universities of China(No.NS2014036)
文摘Abstract To improve the reliability of spaceborne electronic systems, a fault-tolerant strategy of selective triple modular redundancy （STMR） based on multi-objective optimization and evolvable hardware （EHW） against single-event upsets （SEUs） for circuits implemented on field pro- grammable gate arrays （FPGAs） based on static random access memory （SRAM） is presented in this paper. Various topologies of circuit with the same functionality are evolved using EHW firstly. Then the SEU-sensitive gates of each circuit are identified using signal probabilities of all the lines in it, and each circuit is hardened against SEUs by selectively applying triple modular redundancy （TMR） to these SEU-sensitive gates. Afterward, each circuit hardened has been evaluated by SEU Simulation, and the multi-objective optimization technology is introduced to optimize the area overhead and the number of functional errors of all the circuits, The proposed fault-tolerant strategy is tested on four circuits from microelectronics center of North Carolina （MCNC） benchmark suite. The experimental results show that it can generate innovative trade-off solutions to compromise between hardware resource consumption and system reliability. The maximum savings in the area overhead of the STMR circuit over the full TMR design is 58% with the same SEU immunity.
