In deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories more vulnerable to reliability problems, such as soft errors induced by radiation. Error Correction Code(ECC) along w...In deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories more vulnerable to reliability problems, such as soft errors induced by radiation. Error Correction Code(ECC) along with scrubbing is an efficient method for protecting memories against these errors. However, the latency of coding circuits brings speed penalties in high performance applications. This paper proposed a "bit bypassing" ECC protected memory by buffering the encoded data and adding an identifying address for the input data. The proposed memory design has been fabricated on a 130 nm CMOS process. According to the measurement, the proposed scheme only gives the minimum delay overhead of 22.6%, compared with other corresponding memories. Furthermore, heavy ion testing demonstrated the single event effects performance of the proposed memory achieves error rate reductions by 42.9 to 63.3 times.展开更多
Three-party password authenticated key exchange (3PAKE) protocol plays a significant role in the history of secure communication area in which two clients agree a robust session key in an authentic manner based on pas...Three-party password authenticated key exchange (3PAKE) protocol plays a significant role in the history of secure communication area in which two clients agree a robust session key in an authentic manner based on passwords. In recent years, researchers focused on developing simple 3PAKE (S-3PAKE) protocol to gain system e?ciency while preserving security robustness for the system. In this study, we first demonstrate how an undetectable on-line dictionary attack can be successfully applied over three existing S-3PAKE schemes. An error correction code (ECC) based S-3PAKE protocol is then introduced to eliminate the identified authentication weakness.展开更多
With continuous technology scaling, on-chip structures are becoming more and more susceptible to soft errors. Architectural vulnerability factor （AVF） has been introduced to quantify the architectural vulnerability ...With continuous technology scaling, on-chip structures are becoming more and more susceptible to soft errors. Architectural vulnerability factor （AVF） has been introduced to quantify the architectural vulnerability of on-chip structures to soft errors. Recent studies have found that designing soft error protection techniques with the awareness of AVF is greatly helpful to achieve a tradeoff between performance and reliability for several structures （i.e., issue queue, reorder buffer）. Cache is one of the most susceptible components to soft errors and is commonly protected with error correcting codes （ECC）. However, protecting caches closer to the processor （i.e., L1 data cache （LID）） using ECC could result in high overhead. Protecting caches without accurate knowledge of the vulnerability characteristics may lead to over-protection. Therefore, designing AVF-aware ECC is attractive for designers to balance among performance, power and reliability for cache, especially at early design stage. In this paper, we improve the methodology of cache AVF computation and develop a new AVF estimation framework, soft error reliability analysis based on SimpleScalar. Then we characterize dynamic vulnerability behavior of LID and detect the correlations between L1D AVF and various performance metrics. We propose to employ Bayesian additive regression trees to accurately model the variation of L1D AVF and to quantitatively explain the important effects of several key performance metrics on L1D AVF. Then, we employ bump hunting technique to reduce the complexity of L1D AVF prediction and extract some simple selecting rules based on several key performance metrics, thus enabling a simplified and fast estimation of L1D AVF. Based on the simplified and fast estimation of L1D AVF, intervals of high L1D AVF can be identified online, enabling us to develop the AVF-aware ECC technique to reduce the overhead of ECC. Experimental results show that compared with traditional ECC technique which provides complete ECC protection throughout the entire lifetime of a program, AVF-aware ECC technique reduces the L1D access latency by 35% and saves power consumption by 14% for SPEC2K benchmarks averagely.展开更多
基金Supported by the National Science and Technology Major Project of China(No.2013ZX03006004)
文摘In deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories more vulnerable to reliability problems, such as soft errors induced by radiation. Error Correction Code(ECC) along with scrubbing is an efficient method for protecting memories against these errors. However, the latency of coding circuits brings speed penalties in high performance applications. This paper proposed a "bit bypassing" ECC protected memory by buffering the encoded data and adding an identifying address for the input data. The proposed memory design has been fabricated on a 130 nm CMOS process. According to the measurement, the proposed scheme only gives the minimum delay overhead of 22.6%, compared with other corresponding memories. Furthermore, heavy ion testing demonstrated the single event effects performance of the proposed memory achieves error rate reductions by 42.9 to 63.3 times.
基金the National Science Council (Nos. NSC 99-2218-E-011-014 and NSC 100-2219-E-011-002)
文摘Three-party password authenticated key exchange (3PAKE) protocol plays a significant role in the history of secure communication area in which two clients agree a robust session key in an authentic manner based on passwords. In recent years, researchers focused on developing simple 3PAKE (S-3PAKE) protocol to gain system e?ciency while preserving security robustness for the system. In this study, we first demonstrate how an undetectable on-line dictionary attack can be successfully applied over three existing S-3PAKE schemes. An error correction code (ECC) based S-3PAKE protocol is then introduced to eliminate the identified authentication weakness.
基金Supported by the National Natural Science Foundation of China under Grant Nos. 60970036 and 60873016the National High Technology Development 863 Program of China under Grant Nos. 2009AA01Z102 and 2009AA01Z124
文摘With continuous technology scaling, on-chip structures are becoming more and more susceptible to soft errors. Architectural vulnerability factor （AVF） has been introduced to quantify the architectural vulnerability of on-chip structures to soft errors. Recent studies have found that designing soft error protection techniques with the awareness of AVF is greatly helpful to achieve a tradeoff between performance and reliability for several structures （i.e., issue queue, reorder buffer）. Cache is one of the most susceptible components to soft errors and is commonly protected with error correcting codes （ECC）. However, protecting caches closer to the processor （i.e., L1 data cache （LID）） using ECC could result in high overhead. Protecting caches without accurate knowledge of the vulnerability characteristics may lead to over-protection. Therefore, designing AVF-aware ECC is attractive for designers to balance among performance, power and reliability for cache, especially at early design stage. In this paper, we improve the methodology of cache AVF computation and develop a new AVF estimation framework, soft error reliability analysis based on SimpleScalar. Then we characterize dynamic vulnerability behavior of LID and detect the correlations between L1D AVF and various performance metrics. We propose to employ Bayesian additive regression trees to accurately model the variation of L1D AVF and to quantitatively explain the important effects of several key performance metrics on L1D AVF. Then, we employ bump hunting technique to reduce the complexity of L1D AVF prediction and extract some simple selecting rules based on several key performance metrics, thus enabling a simplified and fast estimation of L1D AVF. Based on the simplified and fast estimation of L1D AVF, intervals of high L1D AVF can be identified online, enabling us to develop the AVF-aware ECC technique to reduce the overhead of ECC. Experimental results show that compared with traditional ECC technique which provides complete ECC protection throughout the entire lifetime of a program, AVF-aware ECC technique reduces the L1D access latency by 35% and saves power consumption by 14% for SPEC2K benchmarks averagely.
