This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the perfo...This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the performance of these structures with STSCL (Sub-threshold SCL). The first design under consideration is DTPMOS as load device which analyses the performance of Dynamic Threshold SCL (DTSCL) Logic with previous source coupled logic for ultra low power operation. DTSCL circuits exhibit a better power-delay Performance compared with the STSCL Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The second design under consideration uses basic current mirror active load device to provide required voltage swing. Current mirror source coupled logic (CMSCL) can be used for high speed operation. The advantage of this design is that it provides 54% reduction in power delay product over conventional STSCL. The main drawback of this design is that it provides a higher power dissipation compared to other source coupled logic structures. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control over power dissipation. Measurements of test structures simulated in 0.18 μm CMOS technology shows that the proposed DTSCL logic concept can be utilized successfully for bias currents as low as 1 pA. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits. Cadence Virtuoso schematic editor and Spectre Simulation tools have been used.展开更多
An ultra low voltage rectifier with high power conversion efficiency （PCE） for PE energy harvesting ap- plications is presented in this paper. This is achieved by utilizing the DTMOS which the body terminal is conne...An ultra low voltage rectifier with high power conversion efficiency （PCE） for PE energy harvesting ap- plications is presented in this paper. This is achieved by utilizing the DTMOS which the body terminal is connected to the gate terminal in a diode connected transistor. This implementation facilitates the rectifier with dynamic con- trol over the threshold voltage. Moreover, we use input powered to take the place of output powered to reduce the power loss and thereby increasing the power conversion efficiency. Based on standard SMIC 0.18 μm CMOS tech- nology, the simulation results show that the voltage conversion efficiency and the power conversion efficiency can reach up to 90.5% and 95.5% respectively, when the input voltage equals to 0.2 V @ 100 Hz with load resistance 50 kW. Input voltages with frequencies in the range of 10 Hz-1 kHz can be rectified.展开更多
文摘This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the performance of these structures with STSCL (Sub-threshold SCL). The first design under consideration is DTPMOS as load device which analyses the performance of Dynamic Threshold SCL (DTSCL) Logic with previous source coupled logic for ultra low power operation. DTSCL circuits exhibit a better power-delay Performance compared with the STSCL Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The second design under consideration uses basic current mirror active load device to provide required voltage swing. Current mirror source coupled logic (CMSCL) can be used for high speed operation. The advantage of this design is that it provides 54% reduction in power delay product over conventional STSCL. The main drawback of this design is that it provides a higher power dissipation compared to other source coupled logic structures. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control over power dissipation. Measurements of test structures simulated in 0.18 μm CMOS technology shows that the proposed DTSCL logic concept can be utilized successfully for bias currents as low as 1 pA. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits. Cadence Virtuoso schematic editor and Spectre Simulation tools have been used.
基金supported by the National Natural Science Foundation of China(Nos.61234002,61322405,61306044,61376033)the National High-Tech Program of China(No.2013AA014103)
文摘An ultra low voltage rectifier with high power conversion efficiency （PCE） for PE energy harvesting ap- plications is presented in this paper. This is achieved by utilizing the DTMOS which the body terminal is connected to the gate terminal in a diode connected transistor. This implementation facilitates the rectifier with dynamic con- trol over the threshold voltage. Moreover, we use input powered to take the place of output powered to reduce the power loss and thereby increasing the power conversion efficiency. Based on standard SMIC 0.18 μm CMOS tech- nology, the simulation results show that the voltage conversion efficiency and the power conversion efficiency can reach up to 90.5% and 95.5% respectively, when the input voltage equals to 0.2 V @ 100 Hz with load resistance 50 kW. Input voltages with frequencies in the range of 10 Hz-1 kHz can be rectified.
