A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarith...A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarithmic Maximum A Posterior (PSW-log-MAP), the on-chip turbo decoder can decode an information bit by only an average of two clocks per iteration. On the other hand, a high-parallel pipeline Viterbi algorithm is adopted to realize the 256-state convolutional code decoding. The final decoder with an 8×chip-clock (30 72MHz) driving can concurrently process a data rate up to 2 5Mbps of turbo coded sequences and a data rate over 400kbps of convolutional codes. There is no extern memory needed. Test results show that the decoding performance is only 0 2～0 3dB or less lost comparing to float simulation.展开更多
System-on-a-chips with intellectual property cores need a large volume of data for testing. The large volume of test data requires a large testing time and test data memory. Therefore new techniques are needed to opti...System-on-a-chips with intellectual property cores need a large volume of data for testing. The large volume of test data requires a large testing time and test data memory. Therefore new techniques are needed to optimize the test data volume, decrease the testing time, and conquer the ATE memory limitation for SOC designs. This paper presents a new compression method of testing for intellectual property core-based system-on-chip. The proposed method is based on new split- data variable length (SDV) codes that are designed using the split-options along with identification bits in a string of test data. This paper analyses the reduction of test data volume, testing time, run time, size of memory required in ATE and improvement of compression ratio. Experimental results for ISCAS 85 and ISCAS 89 Benchmark circuits show that SDV codes outperform other compression methods with the best compression ratio for test data compression. The decompression architecture for SDV codes is also presented for decoding the implementations of compressed bits. The proposed scheme shows that SDV codes are accessible to any of the variations in the input test data stream.展开更多
针对通信编码轨道电路上道试用过程中,监测系统稳定性需求,提出一种基于控制器局域网络(Controller Area NetWork,CAN)总线的实时数据监测方案。系统采用分布式工控机架构,非侵入式硬件连接方式,确保不影响轨道电路系统的工作。应用智...针对通信编码轨道电路上道试用过程中,监测系统稳定性需求,提出一种基于控制器局域网络(Controller Area NetWork,CAN)总线的实时数据监测方案。系统采用分布式工控机架构,非侵入式硬件连接方式,确保不影响轨道电路系统的工作。应用智能数据分析算法,对列控中心(Train Control Center,TCC)与通信接口单元之间、通信接口单元与移频柜各设备间的CAN总线通信数据进行实时采集和分析,有效实时监测轨道电路系统各关键节点的通信数据质量。研究结果表明,该方案能够有效识别通信数据异常,为系统可靠性评估和故障诊断提供数据支持,具有较高的工程应用价值。展开更多
文摘A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarithmic Maximum A Posterior (PSW-log-MAP), the on-chip turbo decoder can decode an information bit by only an average of two clocks per iteration. On the other hand, a high-parallel pipeline Viterbi algorithm is adopted to realize the 256-state convolutional code decoding. The final decoder with an 8×chip-clock (30 72MHz) driving can concurrently process a data rate up to 2 5Mbps of turbo coded sequences and a data rate over 400kbps of convolutional codes. There is no extern memory needed. Test results show that the decoding performance is only 0 2～0 3dB or less lost comparing to float simulation.
文摘System-on-a-chips with intellectual property cores need a large volume of data for testing. The large volume of test data requires a large testing time and test data memory. Therefore new techniques are needed to optimize the test data volume, decrease the testing time, and conquer the ATE memory limitation for SOC designs. This paper presents a new compression method of testing for intellectual property core-based system-on-chip. The proposed method is based on new split- data variable length (SDV) codes that are designed using the split-options along with identification bits in a string of test data. This paper analyses the reduction of test data volume, testing time, run time, size of memory required in ATE and improvement of compression ratio. Experimental results for ISCAS 85 and ISCAS 89 Benchmark circuits show that SDV codes outperform other compression methods with the best compression ratio for test data compression. The decompression architecture for SDV codes is also presented for decoding the implementations of compressed bits. The proposed scheme shows that SDV codes are accessible to any of the variations in the input test data stream.
文摘针对通信编码轨道电路上道试用过程中,监测系统稳定性需求,提出一种基于控制器局域网络(Controller Area NetWork,CAN)总线的实时数据监测方案。系统采用分布式工控机架构,非侵入式硬件连接方式,确保不影响轨道电路系统的工作。应用智能数据分析算法,对列控中心(Train Control Center,TCC)与通信接口单元之间、通信接口单元与移频柜各设备间的CAN总线通信数据进行实时采集和分析,有效实时监测轨道电路系统各关键节点的通信数据质量。研究结果表明,该方案能够有效识别通信数据异常,为系统可靠性评估和故障诊断提供数据支持,具有较高的工程应用价值。
