Based on the physical characteristics of SiGe material,a new three-dimensional （3D） CMOS IC structure is proposed,in which the first device layer is made of Si material for nMOS devices and the second device layer i...Based on the physical characteristics of SiGe material,a new three-dimensional （3D） CMOS IC structure is proposed,in which the first device layer is made of Si material for nMOS devices and the second device layer is made of Six Ge1- x material for pMOS. The intrinsic performance of ICs with the new structure is then limited by Si nMOS.The electrical characteristics of a Si-SiGe 3D CMOS device and inverter are all simulated and analyzed by MEDICI. The simulation results indicate that the Si-SiGe 3D CMOS ICs are faster than the Si-Si 3D CMOS ICs. The delay time of the 3D Si-SiGe CMOS inverter is 2-3ps,which is shorter than that of the 3D Si-Si CMOS inverter.展开更多
The monolithic integrated micro sensor is an important direction in the fields of integrated circuits and micro sensors. In this paper,a monolithic thermal vacuum sensor based on a micro-hotplate （MHP） and operating...The monolithic integrated micro sensor is an important direction in the fields of integrated circuits and micro sensors. In this paper,a monolithic thermal vacuum sensor based on a micro-hotplate （MHP） and operating under constant bias voltage conditions was designed. A new monolithic integrating mode was proposed,in which the dielectric and passiva- tion layers in standard CMOS processes were used as sensor structure layers,gate polysilicon as the sacrificial layer,and the second polysilicon layer as the sensor heating resistor. Then, the fabricating processes were designed and the monolithic thermal vacuum sensor was fabricated with a 0. 6μm mixed signal CMOS process followed by sacrificial layer etching technology. The measurement results show that the fabricated monolithic vacuum sensor can measure the pressure range of 2- 10^5 Pa and the output voltage is adjustable.展开更多
A wideband monolithic optoelectronic integrated receiver with a high-speed photo-detector,completely compatible with standard CMOS processes,is designed and implemented in 0.6μm standard CMOS technology.The experimen...A wideband monolithic optoelectronic integrated receiver with a high-speed photo-detector,completely compatible with standard CMOS processes,is designed and implemented in 0.6μm standard CMOS technology.The experimental results demonstrate that its performance approaches applicable requirements,where the photo-detector achieves a -3dB frequency of 1.11GHz,and the receiver achieves a 3dB bandwidth of 733MHz and a sensitivity of -9dBm for λ=850nm at BER=10-12.展开更多
A monolithically integrated optoelectronic receiver is presented. A silicon-based photo-diode and receiver circuits are integrated on identical substrates in order to eliminate the parasitics induced by hybrid packagi...A monolithically integrated optoelectronic receiver is presented. A silicon-based photo-diode and receiver circuits are integrated on identical substrates in order to eliminate the parasitics induced by hybrid packaging. Implemented in the present deep sub-micron MS/RF （mixed signal, radio frequency） CMOS,this monolithically OEIC takes advantage of several new features to improve the performance of the photo-diode and eventually the whole OEIC.展开更多
An integrated 3.3V/1.2V SC DC-DC converter operating under 10MHz with a fixed duty radio of 0.5 is presented.To improve the output current of the converter,CMOS technology is adopted to fabricate the switching devices...An integrated 3.3V/1.2V SC DC-DC converter operating under 10MHz with a fixed duty radio of 0.5 is presented.To improve the output current of the converter,CMOS technology is adopted to fabricate the switching devices,and mutually compensatory circuitry technology is also employed to double the output current furthermore.The simulation results using Hspice simulation software,show that the output currents of a single unit circuit and two unit circuits connected in a mutually compensatory manner of the improved converter is about 12.5mA and 26mA,respectively.The power conversion efficiency of the mutually compensatory circuit can amount to 73%,while its output voltage ripple is less than 1.5%.The converter is fabricated in standard Rohm 0.35μm CMOS technology in Tokyo University of Japan.The test result indicates that the output current of 9.8mA can be obtained from a single unit circuit of the improved converter.展开更多
该文首次报道了一种极简构架的5G毫米波反向阵设计原理及其CMOS芯片实现技术。该毫米波反向阵极简构架,利用次谐波混频器提供相位共轭和阵列反向功能,无需移相电路及波束控制系统,便可实现波束自动回溯移动通信功能。该文采用国产0.18μ...该文首次报道了一种极简构架的5G毫米波反向阵设计原理及其CMOS芯片实现技术。该毫米波反向阵极简构架,利用次谐波混频器提供相位共轭和阵列反向功能,无需移相电路及波束控制系统,便可实现波束自动回溯移动通信功能。该文采用国产0.18μm CMOS工艺研制了5G毫米波反向阵芯片,包括发射前端、接收前端及跟踪锁相环等核心模块,其中发射及接收前端芯片采用次谐波混频及跨导增强等技术,分别实现了19.5 d B和18.7 d B的实测转换增益。所实现的跟踪锁相环芯片具备双模工作优势,可根据不同参考信号支持幅度调制及相位调制,实测输出信号相噪优于–125 dBc/Hz@100 kHz。该文给出的测试结果验证了所提5G毫米波反向阵通信架构及其CMOS芯片实现的可行性,从而为5G/6G毫米波通信探索了一种架构极简、成本极低、拓展性强的新方案。展开更多
In this work,we demonstrate the technology of wafer-scale transistor-level heterogeneous integration of Ga As pseudomorphic high electron mobility transistors（p HEMTs） and Si complementary metal–oxide semiconductor...In this work,we demonstrate the technology of wafer-scale transistor-level heterogeneous integration of Ga As pseudomorphic high electron mobility transistors（p HEMTs） and Si complementary metal–oxide semiconductor（CMOS） on the same Silicon substrate.Ga As p HEMTs are vertical stacked at the top of the Si CMOS wafer using a wafer bonding technique,and the best alignment accuracy of 5 μm is obtained.As a circuit example,a wide band Ga As digital controlled switch is fabricated,which features the technologies of a digital control circuit in Si CMOS and a switch circuit in Ga As p HEMT,15% smaller than the area of normal Ga As and Si CMOS circuits.展开更多
高增益CMOS运算放大器在集成电路设计中扮演着重要角色。CMOS运算放大器具有高增益特性,能够放大微弱的信号,并在电路中提供稳定的放大功能。提出了一种新型高增益CMOS运算放大器的设计方案,由4个三端NMOS管和4个三端PMOS管共同构成,通...高增益CMOS运算放大器在集成电路设计中扮演着重要角色。CMOS运算放大器具有高增益特性,能够放大微弱的信号,并在电路中提供稳定的放大功能。提出了一种新型高增益CMOS运算放大器的设计方案,由4个三端NMOS管和4个三端PMOS管共同构成,通过优化电路结构和参数配置,结合了负反馈和级联放大器的优势,实现了较高的增益和性能指标。该运算放大器采用0.18 um CMOS工艺设计,仿真结果表明,在电压为1.8 V,负载电容为60 pF的环境下,该运算放大器的开环直流增益为81dB,增益带宽为110 M H z,相位裕度为72.9°,电源抑制比110 dB,电源总功耗仅为55 uW。大大提升了运放的增益,降低了电路的功耗并节省了面积。展开更多
A CMOS integrated signal processing circuit based on capacitance resonance principle whose structure is simple in capacitive sensors is designed. The waveform of output voltage is improved by choosing bootstrap refere...A CMOS integrated signal processing circuit based on capacitance resonance principle whose structure is simple in capacitive sensors is designed. The waveform of output voltage is improved by choosing bootstrap reference current mirror with initiate circuit, CMOS analogy switch and positive feedback of double-stage inverter in the circuit. Output voltage of this circuit is a symmetric square wave signal. The variation of sensitive capacitance, which is part of the capacitive sensors, can be denoted by the change of output vohage＇s frequency. The whole circuit is designed with 1.5 μm P-weU CMOS process and simulated by PSpice software. Output frequency varies from 261.05 kHz to 47. 93 kHz if capacitance varies in the range of 1PF - 15PF. And the variation of frequency can be easily detected using counter or SCU.展开更多
Analyzing the influence on Q factor, which was caused by the parasitic effect in a CMOS RF on chip integrated inductor, a concise method to increase the Q factor has been obtained when optimizing the layout parameter....Analyzing the influence on Q factor, which was caused by the parasitic effect in a CMOS RF on chip integrated inductor, a concise method to increase the Q factor has been obtained when optimizing the layout parameter. Using this method, the Q factor of 7.9 can be achieved in a 5nH inductor (operating frequency is 2GHz) while the errors in inductance are less than 0.5% compared with the aimed values. It is proved by experiments that this method can guarantee the sufficient accuracy but require less computation time. Therefore, it is of great use for the design of the inductor in CMOS RF IC’s.展开更多
文摘Based on the physical characteristics of SiGe material,a new three-dimensional （3D） CMOS IC structure is proposed,in which the first device layer is made of Si material for nMOS devices and the second device layer is made of Six Ge1- x material for pMOS. The intrinsic performance of ICs with the new structure is then limited by Si nMOS.The electrical characteristics of a Si-SiGe 3D CMOS device and inverter are all simulated and analyzed by MEDICI. The simulation results indicate that the Si-SiGe 3D CMOS ICs are faster than the Si-Si 3D CMOS ICs. The delay time of the 3D Si-SiGe CMOS inverter is 2-3ps,which is shorter than that of the 3D Si-Si CMOS inverter.
文摘The monolithic integrated micro sensor is an important direction in the fields of integrated circuits and micro sensors. In this paper,a monolithic thermal vacuum sensor based on a micro-hotplate （MHP） and operating under constant bias voltage conditions was designed. A new monolithic integrating mode was proposed,in which the dielectric and passiva- tion layers in standard CMOS processes were used as sensor structure layers,gate polysilicon as the sacrificial layer,and the second polysilicon layer as the sensor heating resistor. Then, the fabricating processes were designed and the monolithic thermal vacuum sensor was fabricated with a 0. 6μm mixed signal CMOS process followed by sacrificial layer etching technology. The measurement results show that the fabricated monolithic vacuum sensor can measure the pressure range of 2- 10^5 Pa and the output voltage is adjustable.
文摘A wideband monolithic optoelectronic integrated receiver with a high-speed photo-detector,completely compatible with standard CMOS processes,is designed and implemented in 0.6μm standard CMOS technology.The experimental results demonstrate that its performance approaches applicable requirements,where the photo-detector achieves a -3dB frequency of 1.11GHz,and the receiver achieves a 3dB bandwidth of 733MHz and a sensitivity of -9dBm for λ=850nm at BER=10-12.
文摘A monolithically integrated optoelectronic receiver is presented. A silicon-based photo-diode and receiver circuits are integrated on identical substrates in order to eliminate the parasitics induced by hybrid packaging. Implemented in the present deep sub-micron MS/RF （mixed signal, radio frequency） CMOS,this monolithically OEIC takes advantage of several new features to improve the performance of the photo-diode and eventually the whole OEIC.
文摘An integrated 3.3V/1.2V SC DC-DC converter operating under 10MHz with a fixed duty radio of 0.5 is presented.To improve the output current of the converter,CMOS technology is adopted to fabricate the switching devices,and mutually compensatory circuitry technology is also employed to double the output current furthermore.The simulation results using Hspice simulation software,show that the output currents of a single unit circuit and two unit circuits connected in a mutually compensatory manner of the improved converter is about 12.5mA and 26mA,respectively.The power conversion efficiency of the mutually compensatory circuit can amount to 73%,while its output voltage ripple is less than 1.5%.The converter is fabricated in standard Rohm 0.35μm CMOS technology in Tokyo University of Japan.The test result indicates that the output current of 9.8mA can be obtained from a single unit circuit of the improved converter.
文摘该文首次报道了一种极简构架的5G毫米波反向阵设计原理及其CMOS芯片实现技术。该毫米波反向阵极简构架,利用次谐波混频器提供相位共轭和阵列反向功能,无需移相电路及波束控制系统,便可实现波束自动回溯移动通信功能。该文采用国产0.18μm CMOS工艺研制了5G毫米波反向阵芯片,包括发射前端、接收前端及跟踪锁相环等核心模块,其中发射及接收前端芯片采用次谐波混频及跨导增强等技术,分别实现了19.5 d B和18.7 d B的实测转换增益。所实现的跟踪锁相环芯片具备双模工作优势,可根据不同参考信号支持幅度调制及相位调制,实测输出信号相噪优于–125 dBc/Hz@100 kHz。该文给出的测试结果验证了所提5G毫米波反向阵通信架构及其CMOS芯片实现的可行性,从而为5G/6G毫米波通信探索了一种架构极简、成本极低、拓展性强的新方案。
文摘In this work,we demonstrate the technology of wafer-scale transistor-level heterogeneous integration of Ga As pseudomorphic high electron mobility transistors（p HEMTs） and Si complementary metal–oxide semiconductor（CMOS） on the same Silicon substrate.Ga As p HEMTs are vertical stacked at the top of the Si CMOS wafer using a wafer bonding technique,and the best alignment accuracy of 5 μm is obtained.As a circuit example,a wide band Ga As digital controlled switch is fabricated,which features the technologies of a digital control circuit in Si CMOS and a switch circuit in Ga As p HEMT,15% smaller than the area of normal Ga As and Si CMOS circuits.
文摘高增益CMOS运算放大器在集成电路设计中扮演着重要角色。CMOS运算放大器具有高增益特性,能够放大微弱的信号,并在电路中提供稳定的放大功能。提出了一种新型高增益CMOS运算放大器的设计方案,由4个三端NMOS管和4个三端PMOS管共同构成,通过优化电路结构和参数配置,结合了负反馈和级联放大器的优势,实现了较高的增益和性能指标。该运算放大器采用0.18 um CMOS工艺设计,仿真结果表明,在电压为1.8 V,负载电容为60 pF的环境下,该运算放大器的开环直流增益为81dB,增益带宽为110 M H z,相位裕度为72.9°,电源抑制比110 dB,电源总功耗仅为55 uW。大大提升了运放的增益,降低了电路的功耗并节省了面积。
文摘A CMOS integrated signal processing circuit based on capacitance resonance principle whose structure is simple in capacitive sensors is designed. The waveform of output voltage is improved by choosing bootstrap reference current mirror with initiate circuit, CMOS analogy switch and positive feedback of double-stage inverter in the circuit. Output voltage of this circuit is a symmetric square wave signal. The variation of sensitive capacitance, which is part of the capacitive sensors, can be denoted by the change of output vohage＇s frequency. The whole circuit is designed with 1.5 μm P-weU CMOS process and simulated by PSpice software. Output frequency varies from 261.05 kHz to 47. 93 kHz if capacitance varies in the range of 1PF - 15PF. And the variation of frequency can be easily detected using counter or SCU.
文摘Analyzing the influence on Q factor, which was caused by the parasitic effect in a CMOS RF on chip integrated inductor, a concise method to increase the Q factor has been obtained when optimizing the layout parameter. Using this method, the Q factor of 7.9 can be achieved in a 5nH inductor (operating frequency is 2GHz) while the errors in inductance are less than 0.5% compared with the aimed values. It is proved by experiments that this method can guarantee the sufficient accuracy but require less computation time. Therefore, it is of great use for the design of the inductor in CMOS RF IC’s.
