With the increase in the quantity and scale of Static Random-Access Memory Field Programmable Gate Arrays (SRAM-based FPGAs) for aerospace application, the volume of FPGA configuration bit files that must be stored ha...With the increase in the quantity and scale of Static Random-Access Memory Field Programmable Gate Arrays (SRAM-based FPGAs) for aerospace application, the volume of FPGA configuration bit files that must be stored has increased dramatically. The use of compression techniques for these bitstream files is emerging as a key strategy to alleviate the burden on storage resources. Due to the severe resource constraints of space-based electronics and the unique application environment, the simplicity, efficiency and robustness of the decompression circuitry is also a key design consideration. Through comparative analysis current bitstream file compression technologies, this research suggests that the Lempel Ziv Oberhumer (LZO) compression algorithm is more suitable for satellite applications. This paper also delves into the compression process and format of the LZO compression algorithm, as well as the inherent characteristics of configuration bitstream files. We propose an improved algorithm based on LZO for bitstream file compression, which optimises the compression process by refining the format and reducing the offset. Furthermore, a low-cost, robust decompression hardware architecture is proposed based on this method. Experimental results show that the compression speed of the improved LZO algorithm is increased by 3%, the decompression hardware cost is reduced by approximately 60%, and the compression ratio is slightly reduced by 0.47%.展开更多
For an SOI-FPGA （silicon-on-insulator field programmable gate arrays） （VS1000） fabricated with 0.5 ttm SOI-CMOS （silicon-on-insulator complementary-metal-oxide-semiconductor） process, a complete integrated platf...For an SOI-FPGA （silicon-on-insulator field programmable gate arrays） （VS1000） fabricated with 0.5 ttm SOI-CMOS （silicon-on-insulator complementary-metal-oxide-semiconductor） process, a complete integrated platform of FPGA computer-aided design （CAD） toolset （VDK） is developed, which can convert the Verilog HDL （hardware description language） description into a bitstream and finally download it into an FPGA. Experiments and testing verify that this FPGA CAD works well and efficiently.展开更多
基金supported in part by the National Key Laboratory of Science and Technology on Space Microwave(Grant Nos.HTKJ2022KL504009 and HTKJ2022KL5040010).
文摘With the increase in the quantity and scale of Static Random-Access Memory Field Programmable Gate Arrays (SRAM-based FPGAs) for aerospace application, the volume of FPGA configuration bit files that must be stored has increased dramatically. The use of compression techniques for these bitstream files is emerging as a key strategy to alleviate the burden on storage resources. Due to the severe resource constraints of space-based electronics and the unique application environment, the simplicity, efficiency and robustness of the decompression circuitry is also a key design consideration. Through comparative analysis current bitstream file compression technologies, this research suggests that the Lempel Ziv Oberhumer (LZO) compression algorithm is more suitable for satellite applications. This paper also delves into the compression process and format of the LZO compression algorithm, as well as the inherent characteristics of configuration bitstream files. We propose an improved algorithm based on LZO for bitstream file compression, which optimises the compression process by refining the format and reducing the offset. Furthermore, a low-cost, robust decompression hardware architecture is proposed based on this method. Experimental results show that the compression speed of the improved LZO algorithm is increased by 3%, the decompression hardware cost is reduced by approximately 60%, and the compression ratio is slightly reduced by 0.47%.
文摘For an SOI-FPGA （silicon-on-insulator field programmable gate arrays） （VS1000） fabricated with 0.5 ttm SOI-CMOS （silicon-on-insulator complementary-metal-oxide-semiconductor） process, a complete integrated platform of FPGA computer-aided design （CAD） toolset （VDK） is developed, which can convert the Verilog HDL （hardware description language） description into a bitstream and finally download it into an FPGA. Experiments and testing verify that this FPGA CAD works well and efficiently.
