This paper aims to discuss how to effectively suppress intersymbol interference by optimizing the filter design, so as to achieve a distortion-free output effect, and effectively compensate the transmission characteri...This paper aims to discuss how to effectively suppress intersymbol interference by optimizing the filter design, so as to achieve a distortion-free output effect, and effectively compensate the transmission characteristics of the baseband transmission system in a non-ideal channel environment, so as to minimize the impact of intersymbol crosser. The simulation experiment model of digital optimal baseband transmission and the overall structure of the system are designed based on the Matlab simulation platform, and the parameters of each module in the simulation experiment model are set. The working process and performance of the digital optimal baseband transmission system are simulated, and the conditions and performance of the digital optimal baseband transmission system are verified according to the simulation results.展开更多
Baseband design and implementation for micro/pico base stations （mBS） in 5G ultra-dense network （UDN） is studied. Low cost is an essential requirement for mBS baseband in UDN. Digital baseband cost of ASIC/ASIP （...Baseband design and implementation for micro/pico base stations （mBS） in 5G ultra-dense network （UDN） is studied. Low cost is an essential requirement for mBS baseband in UDN. Digital baseband cost of ASIC/ASIP （Application Specific Integrated Circuit / Instruction-set processor） is of the most uncertainty in roBS system. However. the actual costs and hardware feasibility of the baseband are yet unknown to network deployers and researchers. In this paper, we studied the baseband hardware system design and implementation for low-cost roBS. We analyzed popular baseband algorithms and architectures for both full-digital and hybrid beamforming （BF） for UDN. We then proposed feasible chip-level solutions for the baseband with up to 128-antenna BS system, and estimated their implementation cost. Results show that among lull-digital BF algorithms, zero-forcing is a choice of high performance and low cost; for hybrid BF, 4×32 architecture （32 RF chains） provides good reduction in baseband cost with acceptable performance loss, thus it can be a preferable solution under low cost consider- ation. The proposed system planning method can also be used for the design of other related systems.展开更多
This letter presents a programmable single-chip architecture for Multi-lnput and Multi-Output （M1MO） OFDM baseband receiver. The architecture comprises a Single Instruction Multiple Data （SIMD） DSP core and three ...This letter presents a programmable single-chip architecture for Multi-lnput and Multi-Output （M1MO） OFDM baseband receiver. The architecture comprises a Single Instruction Multiple Data （SIMD） DSP core and three coprocessors that are used for synchronization, FFT and channel decoder. In this MIMO OFDM system, the Zero Correlation Zone （ZCZ） code is used as the synchronization word preamble of packet in the physical layer in order to avoid the interference from other transmitting antennas. Furthermore, a simple channel estimation algorithm is proposed which is appropriate tbr the SIMD DSP computation.展开更多
Precoding and space-time block coding （STBC）techniques using the uniform channel decomposition （UCD）are proposed to improve the bit error rate （BER） of themultiple-antenna communication system, but at a cost of ...Precoding and space-time block coding （STBC）techniques using the uniform channel decomposition （UCD）are proposed to improve the bit error rate （BER） of themultiple-antenna communication system, but at a cost of areduced data rate. In order to achieve a higher overall systemperformance, a novel adaptive transceiver architecture whichflexibly combines both UCD and UCD ＋ STBC technologies isproposed. The channel state information （CSI） feedback pathwas added to the precoder to select which coding method wasto be used, i.e. UCD alone or UCD ＋ STBC. With thesmaller constellation sizes, Matlab simulation results showthat, the adaptive transceiver architecture will select the UCD-only mode under the higher SNR conditions in order to achievea higher bit rate. The UCD ＋ STBC mode will be selectedunder the lower SNR conditions （e. g., SNR 〈 10 dB） inorder to maintain good BER performance at the cost of areduced data rate. This architecture was implemented andverified using both UMC 0.18 ASIC process technology and aXilinx xc4vlx Virtex-4 FPGA at 150 MHz. The simulationresults demonstrate that the required number of reconfigurablearithmetic unit slices grows linearly with the channel matrixsize, while the number of adder array unit and reconfigurablelogic unit slices increases slightly with the constellation size.展开更多
At present what are the key points focused in the research of loop-delay estimation for the digital predistorter in the radio frequency （RF） power amplifier system is reducing its complexity of engineering realizati...At present what are the key points focused in the research of loop-delay estimation for the digital predistorter in the radio frequency （RF） power amplifier system is reducing its complexity of engineering realization and improving anti-jamming ability and computational speed. Besides, opening up its application scope should be contained. For these targets, a novel method including integer loop delay estimation and fractional part is proposed. The integer part applies amplitude-difference summation function and the fractional one adopts the method of finite impulse response （FIR） linear interpolation. The algorithm finds wide applications. What is more, strong anti-jamming ability and low complexity are also its merits. Simulation results support the above opinion. Digital predistortion （DPD） system based on this algorithm achieves good performance.展开更多
There are already several power models to estimate the power consumption of base stations at system level. However, there is so far no model that can predict power consumption of the future base station designs based ...There are already several power models to estimate the power consumption of base stations at system level. However, there is so far no model that can predict power consumption of the future base station designs based on algorithms and hardware selections with insufficient physical information. We present such an energy model for typical base stations. This model can help designers in estimating, evaluating and optimizing energy/power consumption of candidate designs in early design stages. The proposed model is verified by an LTE extreme scenario. The estimated results show that digital front-end, channel equalization and channel decoding are three major power greedy modules(consuming 39.4%, 16.3%, 13.4%) in a digital baseband subsystem. The power estimation error of the proposed power amplifier(PA) power model is 3.5%(macro cell). The major contribution of this paper is that the proposed models can rapidly estimate energy/power consumption of 4G and the future base stations(such as 5G) in early design stages with well acceptable precision, even without sufficient implementation information.展开更多
Baseband ASIP designs for handsets are discussed based on the author's R&D backgrounds. Algorithms for 4G, 3G, and WLAN are analyzed and selected for implementation based on the trade off of cost and performan...Baseband ASIP designs for handsets are discussed based on the author's R&D backgrounds. Algorithms for 4G, 3G, and WLAN are analyzed and selected for implementation based on the trade off of cost and performance with power consumption in mind. A SDR ASIP baseband system architecture is proposed for 4G and 3G mobile handsets. Function partitions for heterogeneous symbol processors are introduced to get higher performance over cost. Three structures for DFE, FFE, and Matrix symbol ASIP are proposed. The concept of bit parallel processor is introduced. Challenges of baseband processors for UDN of 5G were briefly introduced. Conclusions on ASIP architecture and system design are given for different baseband processors on different products.展开更多
The Chaotic Baseband Wireless Communication System(CBWCS)is expected to eliminate the Inter-Symbol Interference(ISI)caused by multipath propagation by using the optimal decoding threshold that is the sum of the ISI ca...The Chaotic Baseband Wireless Communication System(CBWCS)is expected to eliminate the Inter-Symbol Interference(ISI)caused by multipath propagation by using the optimal decoding threshold that is the sum of the ISI caused by past decoded bits and the ISI caused by future transmitting bits.However,the current technique is only capable of removing partial effects of the ISI,because only past decoded bits are available for the suboptimal decoding threshold calculation.The unavailability of the future information needed for the optimal decoding threshold is an obstacle to further improve the Bit Error Rate(BER)performance.In contrast to the previous method using Echo State Network(ESN)to predict one future bit,the proposed method in this paper predicts the optimal decoding threshold directly using ESN.The proposed ESN-based threshold prediction method simplifies the symbol decoding operation by avoiding the iterative prediction of the output waveform points using ESN and accumulated error caused by the iterative operation.With this approach,the calculation complexity is reduced compared to the previous ESN-based approach.The proposed method achieves better BER performance compared to the previous method.The reason for this superior result is twofold.First,the proposed ESN is capable of using more future symbols information conveyed by the ESN input to obtain more accurate threshold rather than the previous method in which only one future symbol was available.Second,the proposed method here does not need to estimate the channel information using Least Squared(LS)method,which avoids the extra error caused by inaccurate channel information estimation.Simulation results and experiment based on a wireless open-access research platform under a practical wireless channel show the effectiveness and superiority of the proposed method.展开更多
The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power...The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.展开更多
文摘This paper aims to discuss how to effectively suppress intersymbol interference by optimizing the filter design, so as to achieve a distortion-free output effect, and effectively compensate the transmission characteristics of the baseband transmission system in a non-ideal channel environment, so as to minimize the impact of intersymbol crosser. The simulation experiment model of digital optimal baseband transmission and the overall structure of the system are designed based on the Matlab simulation platform, and the parameters of each module in the simulation experiment model are set. The working process and performance of the digital optimal baseband transmission system are simulated, and the conditions and performance of the digital optimal baseband transmission system are verified according to the simulation results.
基金supporting from National High Technical Research and Development Program of China(863 program)2014AA01A705 is sincerely acknowledged by authors
文摘Baseband design and implementation for micro/pico base stations （mBS） in 5G ultra-dense network （UDN） is studied. Low cost is an essential requirement for mBS baseband in UDN. Digital baseband cost of ASIC/ASIP （Application Specific Integrated Circuit / Instruction-set processor） is of the most uncertainty in roBS system. However. the actual costs and hardware feasibility of the baseband are yet unknown to network deployers and researchers. In this paper, we studied the baseband hardware system design and implementation for low-cost roBS. We analyzed popular baseband algorithms and architectures for both full-digital and hybrid beamforming （BF） for UDN. We then proposed feasible chip-level solutions for the baseband with up to 128-antenna BS system, and estimated their implementation cost. Results show that among lull-digital BF algorithms, zero-forcing is a choice of high performance and low cost; for hybrid BF, 4×32 architecture （32 RF chains） provides good reduction in baseband cost with acceptable performance loss, thus it can be a preferable solution under low cost consider- ation. The proposed system planning method can also be used for the design of other related systems.
基金Supported by the National Natural Science Foundation of China (No.60476013).
文摘This letter presents a programmable single-chip architecture for Multi-lnput and Multi-Output （M1MO） OFDM baseband receiver. The architecture comprises a Single Instruction Multiple Data （SIMD） DSP core and three coprocessors that are used for synchronization, FFT and channel decoder. In this MIMO OFDM system, the Zero Correlation Zone （ZCZ） code is used as the synchronization word preamble of packet in the physical layer in order to avoid the interference from other transmitting antennas. Furthermore, a simple channel estimation algorithm is proposed which is appropriate tbr the SIMD DSP computation.
基金The National Natural Science Foundation of China(No.61376025)the Industry-Academic Joint Technological Innovations FundP roject of Jiangsu(No.BY2013003-11)the Scientific Innovation Research of College Graduates in Jiangsu Province(No.KYLX_0273)
文摘Precoding and space-time block coding （STBC）techniques using the uniform channel decomposition （UCD）are proposed to improve the bit error rate （BER） of themultiple-antenna communication system, but at a cost of areduced data rate. In order to achieve a higher overall systemperformance, a novel adaptive transceiver architecture whichflexibly combines both UCD and UCD ＋ STBC technologies isproposed. The channel state information （CSI） feedback pathwas added to the precoder to select which coding method wasto be used, i.e. UCD alone or UCD ＋ STBC. With thesmaller constellation sizes, Matlab simulation results showthat, the adaptive transceiver architecture will select the UCD-only mode under the higher SNR conditions in order to achievea higher bit rate. The UCD ＋ STBC mode will be selectedunder the lower SNR conditions （e. g., SNR 〈 10 dB） inorder to maintain good BER performance at the cost of areduced data rate. This architecture was implemented andverified using both UMC 0.18 ASIC process technology and aXilinx xc4vlx Virtex-4 FPGA at 150 MHz. The simulationresults demonstrate that the required number of reconfigurablearithmetic unit slices grows linearly with the channel matrixsize, while the number of adder array unit and reconfigurablelogic unit slices increases slightly with the constellation size.
基金supported by the Circuit and System Foremost Discipline of Zhejiang Province under Grant No. ZZ050103-11
文摘At present what are the key points focused in the research of loop-delay estimation for the digital predistorter in the radio frequency （RF） power amplifier system is reducing its complexity of engineering realization and improving anti-jamming ability and computational speed. Besides, opening up its application scope should be contained. For these targets, a novel method including integer loop delay estimation and fractional part is proposed. The integer part applies amplitude-difference summation function and the fractional one adopts the method of finite impulse response （FIR） linear interpolation. The algorithm finds wide applications. What is more, strong anti-jamming ability and low complexity are also its merits. Simulation results support the above opinion. Digital predistortion （DPD） system based on this algorithm achieves good performance.
基金supporting from National High Technical Research and Development Program of China (863 program) 2014AA01A705
文摘There are already several power models to estimate the power consumption of base stations at system level. However, there is so far no model that can predict power consumption of the future base station designs based on algorithms and hardware selections with insufficient physical information. We present such an energy model for typical base stations. This model can help designers in estimating, evaluating and optimizing energy/power consumption of candidate designs in early design stages. The proposed model is verified by an LTE extreme scenario. The estimated results show that digital front-end, channel equalization and channel decoding are three major power greedy modules(consuming 39.4%, 16.3%, 13.4%) in a digital baseband subsystem. The power estimation error of the proposed power amplifier(PA) power model is 3.5%(macro cell). The major contribution of this paper is that the proposed models can rapidly estimate energy/power consumption of 4G and the future base stations(such as 5G) in early design stages with well acceptable precision, even without sufficient implementation information.
基金supported by the National HighTech Research and Development Program of China (863 Program) 2014AA01A705.
文摘Baseband ASIP designs for handsets are discussed based on the author's R&D backgrounds. Algorithms for 4G, 3G, and WLAN are analyzed and selected for implementation based on the trade off of cost and performance with power consumption in mind. A SDR ASIP baseband system architecture is proposed for 4G and 3G mobile handsets. Function partitions for heterogeneous symbol processors are introduced to get higher performance over cost. Three structures for DFE, FFE, and Matrix symbol ASIP are proposed. The concept of bit parallel processor is introduced. Challenges of baseband processors for UDN of 5G were briefly introduced. Conclusions on ASIP architecture and system design are given for different baseband processors on different products.
文摘The Chaotic Baseband Wireless Communication System(CBWCS)is expected to eliminate the Inter-Symbol Interference(ISI)caused by multipath propagation by using the optimal decoding threshold that is the sum of the ISI caused by past decoded bits and the ISI caused by future transmitting bits.However,the current technique is only capable of removing partial effects of the ISI,because only past decoded bits are available for the suboptimal decoding threshold calculation.The unavailability of the future information needed for the optimal decoding threshold is an obstacle to further improve the Bit Error Rate(BER)performance.In contrast to the previous method using Echo State Network(ESN)to predict one future bit,the proposed method in this paper predicts the optimal decoding threshold directly using ESN.The proposed ESN-based threshold prediction method simplifies the symbol decoding operation by avoiding the iterative prediction of the output waveform points using ESN and accumulated error caused by the iterative operation.With this approach,the calculation complexity is reduced compared to the previous ESN-based approach.The proposed method achieves better BER performance compared to the previous method.The reason for this superior result is twofold.First,the proposed ESN is capable of using more future symbols information conveyed by the ESN input to obtain more accurate threshold rather than the previous method in which only one future symbol was available.Second,the proposed method here does not need to estimate the channel information using Least Squared(LS)method,which avoids the extra error caused by inaccurate channel information estimation.Simulation results and experiment based on a wireless open-access research platform under a practical wireless channel show the effectiveness and superiority of the proposed method.
基金supported in part by the National Natural Science Foundation of China(No.61306027)
文摘The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.
