This paper presents a new topology to implement Class F power amplifier for eliminating the on-resistance (R_(ON))effect.The time-domain and frequency-domain voltage and current waveforms for Class F amplifier are ana...This paper presents a new topology to implement Class F power amplifier for eliminating the on-resistance (R_(ON))effect.The time-domain and frequency-domain voltage and current waveforms for Class F amplifier are ana- lyzed using Fourier series analysis method.Considering the on-resistance effect,the formulas of the efficiency,output power,dc power dissipation,and fundamental load impedance are given from ideal current and voltage waveforms.For experimental verification,we designed and implemented a Class F power amplifier,which operates at 850 MHz using MGaAs/GaAs Heterostructure FET(HFET)device,and analyzed the measurement results.Test results show that the maximum PAE of 67% can be achieved at 28 dBm output power level.展开更多
The fundamental operating principle of a Class F power amplifier and the factors aiding or affecting Class F performance were explicated previously. A Class F power amplifier design which satisfies WCDMA specification...The fundamental operating principle of a Class F power amplifier and the factors aiding or affecting Class F performance were explicated previously. A Class F power amplifier design which satisfies WCDMA specifications is explained in this paper. The Class F amplifier was designed by employing Motorola’s LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor models and we simulated its performance by means of ADS. A variety of procedures were applied in the process of designing Class F amplifier, namely, DC simulation, bias point selection, source-pull and load-pull characterization, input and output matching circuit design and the design of suitable harmonic traps, which are explained here.展开更多
The appearance of third-generation semiconductors represented by gallium nitride （GaN） material greatly improves the output power of a power amplifier （PA）, but the efficiency of the PA needs to be further improve...The appearance of third-generation semiconductors represented by gallium nitride （GaN） material greatly improves the output power of a power amplifier （PA）, but the efficiency of the PA needs to be further improved. The Class-F PA reduces the overlap of drain voltage and current by tuning harmonic impedance so that high efficiency is achieved. This paper begins with the principle of class-F PA, regards the third harmonic voltage as an independent variable, analyzes the influence of the third harmonic on fundamental, and points out how drain efficiency and output power vary with the third harmonic voltage with an I-V knee effect. Finally, the best third harmonic impedance is found mathematically. We compare our results with the Loadpull technique in advanced design system environment and conclude that an optimized third harmonic impedance is open in an ideal case, while it is not at an open point with the I-V knee effect, and the drain efficiency with optimized third harmonic impedance is 4% higher than that with the third harmonic open.展开更多
This paper presents a system-level method to decrease the power consumption of integrated audio Class-G amplifiers for mobile phones by using the same implementation of the level detector, but by changing the paramete...This paper presents a system-level method to decrease the power consumption of integrated audio Class-G amplifiers for mobile phones by using the same implementation of the level detector, but by changing the parameters of the switching algorithm. This method uses an optimization based on a simplified model simulation to quickly find the best power supply switching strategy in order to decrease the losses of the internal Class-AB amplifier. Using a few relevant equations of Class-G on the electrical level and by reducing the number of calculation points, this model can dramatically reduce the calculation time to allow power consumption evaluation in realistic case conditions compared to the currently available tools. This simplified model also evaluates the audio quality reproduction thanks to a psycho-acoustic method. The model has been validated by comparing model results and practical measurements on two industrial circuits. This proposed model is used by an optimizer based on a genetic algorithm associated with a pattern search algorithm to find the best power supply switching strategy for the internal Class-AB amplifier. The optimization results improve life-time performance by saving at least 25% in power consumption for typical use-case (1mW) compared to the industrial circuit studied and without losses in audio quality.展开更多
An X-band inverse class-F power amplifier is realized by a 1-mm Al Ga N/Ga N high electron mobility transistor（HEMT）.The intrinsic and parasitic components inside the transistor,especially output capacitor Cds,influ...An X-band inverse class-F power amplifier is realized by a 1-mm Al Ga N/Ga N high electron mobility transistor（HEMT）.The intrinsic and parasitic components inside the transistor,especially output capacitor Cds,influence the harmonic impedance heavily at the X-band,so compensation design is used for meeting the harmonic condition of inverse class-F on the current source plane.Experiment results show that,in the continuous-wave mode,the power amplifier achieves 61.7% power added efficiency（PAE）,which is 16.3% higher than the class-AB power amplifier realized by the same kind of HEMT.To the best of our knowledge,this is the first inverse class-F Ga N internally-matched power amplifier,and the PAE is quite high at the X-band.展开更多
This paper presents a 1.8 GHz class-E controlled power amplifier (PA). The proposed power amplifier is designed with two-stage architecture. The main advantage of the proposed technique for output control power is a h...This paper presents a 1.8 GHz class-E controlled power amplifier (PA). The proposed power amplifier is designed with two-stage architecture. The main advantage of the proposed technique for output control power is a high 37 dB output power dynamic range with good average power adding efficiency. The measurement results show that the PA achieves a high power gain of 23 dBm and power added efficiency (PAE) by 38%. The circuit was post layout simulated in a standard 0.18 μm CMOS technology.展开更多
This paper presents a brief overview of several promising design technologies for high efficiency silicon-based radio frequency （RF） power amplifiers （PAs） as well as the use of these technologies in mobile broadb...This paper presents a brief overview of several promising design technologies for high efficiency silicon-based radio frequency （RF） power amplifiers （PAs） as well as the use of these technologies in mobile broadband wireless communications. Four important aspects of PA design are addressed in this paper. First, we look at class-E PA design equations and provide an example of a class-E PA that achieves efficiency of 65-70% at 2.4 GHz. Then, we discuss state-of-the-art envelope tracking （ET） design for monolithic wideband RF mobile transmitter applications. A brief overview of Doherty PA design for the next-generation wireless handset applications is then given. Towards the end of the paper, we discuss an inherently broadband and highly efficient class-J PA design targeting future multi-band multi-standard wireless communication protocols.展开更多
This paper presents a high efficiency Doherty power amplifier suitable for TV band applications. A class AB power amplifier is firstly implemented using a commercial GaN HEMT from Cree Incorporation, achieving a high ...This paper presents a high efficiency Doherty power amplifier suitable for TV band applications. A class AB power amplifier is firstly implemented using a commercial GaN HEMT from Cree Incorporation, achieving a high power-added-efficiency of 77.78% and a 40.593 dBm output power with an associated gain of 21.65 dB. The Doherty amplifier has then been designed following the previous class AB scheme for the main amplifier and a class C scheme for the peak one. This amplifier attained a high power-added-efficiency of 81.94%, a 42.77 dBm output power, an associated gain of 21.32 dB, and an operating frequency bandwidth between 550 and 1000 MHz (58.06% fractional bandwidth) which made it suitable for TV band applications.展开更多
To satisfy the design requirements of analog-to-digital converter （ADC） of high speed sampling system in an infrared focal plane array tester with 1024 × 1024 pixels, a first inter-stage amplifier of 12-bit 40-...To satisfy the design requirements of analog-to-digital converter （ADC） of high speed sampling system in an infrared focal plane array tester with 1024 × 1024 pixels, a first inter-stage amplifier of 12-bit 40- Msample/s pipelined ADC was designed with 0. 35 μm CMOS technology. On the basis of traditional two-stage amplifier, the cross-coupled class AB output stage and cascode compensation were adopted to improve the output vohage swing and bandwidth. Power dissipation was optimized with math tools. Circuit and layout design were completed. Simulation results show that the designed amplifier has good performance of 95 dB dc gain, ±2 V output voltage swing, 190 MHz bandwidth and 63° phase margin with feedback factor 1/4, 33 mW power dissipation and so on, which can meet the system requirements.展开更多
A double balanced Gilbert-cell class-A amplifier bleeding mixer (DBGC CAAB mixer) is proposed and implemented. The injection current is utilized to amplify the local oscillator (LO) signal to improve the performance o...A double balanced Gilbert-cell class-A amplifier bleeding mixer (DBGC CAAB mixer) is proposed and implemented. The injection current is utilized to amplify the local oscillator (LO) signal to improve the performance of the transconductor stage. The DBGC CAAB mixer achieves a conversion gain of 17.5 dB at -14 dBm LO power, and the noise figure is suppressed from 45 dB to 10.7 dB. It is important to stress that the new configuration will not drain additional power in contrast to the former current bleeding mixers. This topology dramatically relieves the requirement of the LO power. The DBGC CAAB mixer is implemented by using 0.18-μm RFCMOS technology and operates at the 2.4 GHz ISM application with 10 MHz intermediate frequency. The power consumption is 12 mA at 1.5 V supply voltage. The DBGC CAAB mixer features the highest FOM figure within a wide range of LO power.展开更多
This paper presents a fully integrated CMOS filterless class D amplifier that can directly hook up lithium battery in mobile application The proposed amplifier embodies a 2-order feedback path architecture instead of ...This paper presents a fully integrated CMOS filterless class D amplifier that can directly hook up lithium battery in mobile application The proposed amplifier embodies a 2-order feedback path architecture instead of direct feedback of output to input of the integrator to decrease the high frequency intermodulation distortion associated with direct feedback and eliminate the integrator input common mode disturbance from the output in ternary modulation.The prototype class D amplifier realized in 0.35μm digital technology achieves a THD+N of 0.02%when delivering 400 m W to an 8Ωload from V_(DD)=3.6 V.The PSRR of the prototype class D amplifier is 80 dB at217 Hz.Furthermore a filterless method that can eliminate the external LC filter is employed which offers great advantages of saving PCB space and lowering system cost.In addition the prototype class D amplifier can operate in large voltage range with V_(DD)range from 2.5 to 4.2V in mobile application.The total area of the amplifier is 1.7mm^2.展开更多
文摘This paper presents a new topology to implement Class F power amplifier for eliminating the on-resistance (R_(ON))effect.The time-domain and frequency-domain voltage and current waveforms for Class F amplifier are ana- lyzed using Fourier series analysis method.Considering the on-resistance effect,the formulas of the efficiency,output power,dc power dissipation,and fundamental load impedance are given from ideal current and voltage waveforms.For experimental verification,we designed and implemented a Class F power amplifier,which operates at 850 MHz using MGaAs/GaAs Heterostructure FET(HFET)device,and analyzed the measurement results.Test results show that the maximum PAE of 67% can be achieved at 28 dBm output power level.
文摘The fundamental operating principle of a Class F power amplifier and the factors aiding or affecting Class F performance were explicated previously. A Class F power amplifier design which satisfies WCDMA specifications is explained in this paper. The Class F amplifier was designed by employing Motorola’s LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor models and we simulated its performance by means of ADS. A variety of procedures were applied in the process of designing Class F amplifier, namely, DC simulation, bias point selection, source-pull and load-pull characterization, input and output matching circuit design and the design of suitable harmonic traps, which are explained here.
文摘The appearance of third-generation semiconductors represented by gallium nitride （GaN） material greatly improves the output power of a power amplifier （PA）, but the efficiency of the PA needs to be further improved. The Class-F PA reduces the overlap of drain voltage and current by tuning harmonic impedance so that high efficiency is achieved. This paper begins with the principle of class-F PA, regards the third harmonic voltage as an independent variable, analyzes the influence of the third harmonic on fundamental, and points out how drain efficiency and output power vary with the third harmonic voltage with an I-V knee effect. Finally, the best third harmonic impedance is found mathematically. We compare our results with the Loadpull technique in advanced design system environment and conclude that an optimized third harmonic impedance is open in an ideal case, while it is not at an open point with the I-V knee effect, and the drain efficiency with optimized third harmonic impedance is 4% higher than that with the third harmonic open.
文摘This paper presents a system-level method to decrease the power consumption of integrated audio Class-G amplifiers for mobile phones by using the same implementation of the level detector, but by changing the parameters of the switching algorithm. This method uses an optimization based on a simplified model simulation to quickly find the best power supply switching strategy in order to decrease the losses of the internal Class-AB amplifier. Using a few relevant equations of Class-G on the electrical level and by reducing the number of calculation points, this model can dramatically reduce the calculation time to allow power consumption evaluation in realistic case conditions compared to the currently available tools. This simplified model also evaluates the audio quality reproduction thanks to a psycho-acoustic method. The model has been validated by comparing model results and practical measurements on two industrial circuits. This proposed model is used by an optimizer based on a genetic algorithm associated with a pattern search algorithm to find the best power supply switching strategy for the internal Class-AB amplifier. The optimization results improve life-time performance by saving at least 25% in power consumption for typical use-case (1mW) compared to the industrial circuit studied and without losses in audio quality.
基金Project supported by the National High Technology Research and Development Program of China(Grant No.2015AA016801)
文摘An X-band inverse class-F power amplifier is realized by a 1-mm Al Ga N/Ga N high electron mobility transistor（HEMT）.The intrinsic and parasitic components inside the transistor,especially output capacitor Cds,influence the harmonic impedance heavily at the X-band,so compensation design is used for meeting the harmonic condition of inverse class-F on the current source plane.Experiment results show that,in the continuous-wave mode,the power amplifier achieves 61.7% power added efficiency（PAE）,which is 16.3% higher than the class-AB power amplifier realized by the same kind of HEMT.To the best of our knowledge,this is the first inverse class-F Ga N internally-matched power amplifier,and the PAE is quite high at the X-band.
文摘This paper presents a 1.8 GHz class-E controlled power amplifier (PA). The proposed power amplifier is designed with two-stage architecture. The main advantage of the proposed technique for output control power is a high 37 dB output power dynamic range with good average power adding efficiency. The measurement results show that the PA achieves a high power gain of 23 dBm and power added efficiency (PAE) by 38%. The circuit was post layout simulated in a standard 0.18 μm CMOS technology.
文摘This paper presents a brief overview of several promising design technologies for high efficiency silicon-based radio frequency （RF） power amplifiers （PAs） as well as the use of these technologies in mobile broadband wireless communications. Four important aspects of PA design are addressed in this paper. First, we look at class-E PA design equations and provide an example of a class-E PA that achieves efficiency of 65-70% at 2.4 GHz. Then, we discuss state-of-the-art envelope tracking （ET） design for monolithic wideband RF mobile transmitter applications. A brief overview of Doherty PA design for the next-generation wireless handset applications is then given. Towards the end of the paper, we discuss an inherently broadband and highly efficient class-J PA design targeting future multi-band multi-standard wireless communication protocols.
文摘This paper presents a high efficiency Doherty power amplifier suitable for TV band applications. A class AB power amplifier is firstly implemented using a commercial GaN HEMT from Cree Incorporation, achieving a high power-added-efficiency of 77.78% and a 40.593 dBm output power with an associated gain of 21.65 dB. The Doherty amplifier has then been designed following the previous class AB scheme for the main amplifier and a class C scheme for the peak one. This amplifier attained a high power-added-efficiency of 81.94%, a 42.77 dBm output power, an associated gain of 21.32 dB, and an operating frequency bandwidth between 550 and 1000 MHz (58.06% fractional bandwidth) which made it suitable for TV band applications.
文摘To satisfy the design requirements of analog-to-digital converter （ADC） of high speed sampling system in an infrared focal plane array tester with 1024 × 1024 pixels, a first inter-stage amplifier of 12-bit 40- Msample/s pipelined ADC was designed with 0. 35 μm CMOS technology. On the basis of traditional two-stage amplifier, the cross-coupled class AB output stage and cascode compensation were adopted to improve the output vohage swing and bandwidth. Power dissipation was optimized with math tools. Circuit and layout design were completed. Simulation results show that the designed amplifier has good performance of 95 dB dc gain, ±2 V output voltage swing, 190 MHz bandwidth and 63° phase margin with feedback factor 1/4, 33 mW power dissipation and so on, which can meet the system requirements.
文摘A double balanced Gilbert-cell class-A amplifier bleeding mixer (DBGC CAAB mixer) is proposed and implemented. The injection current is utilized to amplify the local oscillator (LO) signal to improve the performance of the transconductor stage. The DBGC CAAB mixer achieves a conversion gain of 17.5 dB at -14 dBm LO power, and the noise figure is suppressed from 45 dB to 10.7 dB. It is important to stress that the new configuration will not drain additional power in contrast to the former current bleeding mixers. This topology dramatically relieves the requirement of the LO power. The DBGC CAAB mixer is implemented by using 0.18-μm RFCMOS technology and operates at the 2.4 GHz ISM application with 10 MHz intermediate frequency. The power consumption is 12 mA at 1.5 V supply voltage. The DBGC CAAB mixer features the highest FOM figure within a wide range of LO power.
基金supported by the National Natural Science Foundation of China(Nos.61234002,61322405,61306044)
文摘This paper presents a fully integrated CMOS filterless class D amplifier that can directly hook up lithium battery in mobile application The proposed amplifier embodies a 2-order feedback path architecture instead of direct feedback of output to input of the integrator to decrease the high frequency intermodulation distortion associated with direct feedback and eliminate the integrator input common mode disturbance from the output in ternary modulation.The prototype class D amplifier realized in 0.35μm digital technology achieves a THD+N of 0.02%when delivering 400 m W to an 8Ωload from V_(DD)=3.6 V.The PSRR of the prototype class D amplifier is 80 dB at217 Hz.Furthermore a filterless method that can eliminate the external LC filter is employed which offers great advantages of saving PCB space and lowering system cost.In addition the prototype class D amplifier can operate in large voltage range with V_(DD)range from 2.5 to 4.2V in mobile application.The total area of the amplifier is 1.7mm^2.
