A three-stage differential voltage-controlled ring oscillator is presented for wide-tuning and low-phase noise requirement of clock and data recovery circuit in ultra wideband（UWB） wireless body area network. To imp...A three-stage differential voltage-controlled ring oscillator is presented for wide-tuning and low-phase noise requirement of clock and data recovery circuit in ultra wideband（UWB） wireless body area network. To improve the performance of phase noise of delay cell with coarse and fine frequency tuning, injection locked technology together with pseudo differential architecture are adopted. In addition, a multiloop is employed for frequency boosting. Two RVCOs, the standard RVCO without the IL block and the proposed IL RVCO, were fabricated in SMIC 0.18 m 1P6 M Salicide CMOS process. The proposed IL RVCO exhibits a measured phase noise of –112.37 d Bc/Hz at 1 MHz offset from the center frequency of 1 GHz, while dissipating a current of 8 m A excluding the buffer from a 1.8-V supply voltage. It shows a 16.07 d B phase noise improvement at 1 MHz offset compared to the standard topology.展开更多
基金Project supported by the National Natural Science Foundation of China(No.61264001)the Guangxi Natural Science Foundation(Nos.2013GXNSFAA019333,2015GXNSFAA139301,2014GXNSFAA118386)+2 种基金the Graduate Education Innovation Program of GUET(No.GDYCSZ201457)the Project of Guangxi Education Department(No.LD14066B)the High-Level-Innovation Team and Outstanding Scholar Project of Guangxi Higher Education Institutes
文摘A three-stage differential voltage-controlled ring oscillator is presented for wide-tuning and low-phase noise requirement of clock and data recovery circuit in ultra wideband（UWB） wireless body area network. To improve the performance of phase noise of delay cell with coarse and fine frequency tuning, injection locked technology together with pseudo differential architecture are adopted. In addition, a multiloop is employed for frequency boosting. Two RVCOs, the standard RVCO without the IL block and the proposed IL RVCO, were fabricated in SMIC 0.18 m 1P6 M Salicide CMOS process. The proposed IL RVCO exhibits a measured phase noise of –112.37 d Bc/Hz at 1 MHz offset from the center frequency of 1 GHz, while dissipating a current of 8 m A excluding the buffer from a 1.8-V supply voltage. It shows a 16.07 d B phase noise improvement at 1 MHz offset compared to the standard topology.
