Field-effect nanofluidic transistors(FENTs),biomimicking the structure and functionality of neuron,act as biological transistors with the ability to gate switching responses to external stimuli.The switching ratio has...Field-effect nanofluidic transistors(FENTs),biomimicking the structure and functionality of neuron,act as biological transistors with the ability to gate switching responses to external stimuli.The switching ratio has been verified to evaluate the performance of FENTs,but until recently,the response time,another crucial indicator,has been ignored.Employing finite-element method,we investigated the relationship among gate charge,switching ratio and response time by divisionally manipulating gate charge,including entrance surface and the surface of confinement space,for ion transport to optimize switching capability.The dual-split gate charge on FENTs exhibits synergistic effect on switching response.Based on the two regional gate charge on FENTs,multivalence ions in lower concentration,high aspect ratio and single channel show higher switching ratio but longer response time compared to monovalent ions.The findings highlight the necessity of balancing these two signals in FENTs and offer insights for optimizing their design and expanding applications to dual-signal-detection iontronics.展开更多
基于高速低功耗混合应用场景下对互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)比较器性能的综合需求,系统研究其结构优化设计。阐述动态比较器在响应速度、功耗控制、输入失调与噪声抑制等方面的关键技术,介绍...基于高速低功耗混合应用场景下对互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)比较器性能的综合需求,系统研究其结构优化设计。阐述动态比较器在响应速度、功耗控制、输入失调与噪声抑制等方面的关键技术,介绍前置放大器、电源控制、闭环反馈及偏置电路的协同优化策略。结合65 nm CMOS工艺下的仿真测试结果,分析主要性能指标在典型工况下的表现,验证所提结构的可实现性与工程适应性。结果表明,该设计能够在低功耗约束下保持高速响应。展开更多
This study focuses on a 60 V trench MOSFET device designed for operation in space radiation environments.By increasing the bulk region concentration and placing the etched gate trench after the P+implantation process,...This study focuses on a 60 V trench MOSFET device designed for operation in space radiation environments.By increasing the bulk region concentration and placing the etched gate trench after the P+implantation process,we successfully reduced the threshold voltage shift from 6.5 to 2.2 V under a total dose of 400 krad(Si)^(60)Co,allowing the device to operate normally.Structurally,by embedding the source metal in the active and terminal regions,the device demonstrated current degradation without experiencing single-event burnout when subjected to a drain voltage of 60 V and a linear energy transfer value of 75.4 MeV·cm^(2)∕mg from tantalum-ion incidence.TCAD simulations verified that the embedded source metal effectively suppressed parasitic transistor conduction and eliminated the base-region expansion effect,thereby lowering the maximum temperature from 8000 to 1400 K.The irradiation effects of the embedded source metal in the terminal region were also investigated,which can improve the reverse recovery and ensure that the terminal metal does not melt prematurely,thereby significantly enhancing the radiation hardness of the device.展开更多
This paper quantitatively discusses the influence of well contact on single-event transient(SET)in sub-20 nm FinFET by two-photon absorption(TPA)pulse laser.Two groups of inverter chains were designed to investigate t...This paper quantitatively discusses the influence of well contact on single-event transient(SET)in sub-20 nm FinFET by two-photon absorption(TPA)pulse laser.Two groups of inverter chains were designed to investigate the impact of well contact distance on the FinFET process.The experimental results show that the SET pulse width has a bimodal symmetric distribution,which is different from that of a bulk planar CMOS device.To investigate the detailed mechanism of the phenomenon,a high-precision FinFET TCAD model was established,in which both Id-Vd and Id-Vg errors were less than 10%compared to the SPICE model provided by the commercial process.TCAD simulation under heavy ion injection showed the mechanism of the abnormal phenomenon,where the well contact plays a major role in charge collection at the near-well contact distance,while the source plays a major role at the far distance.This phenomenon is completely different from that of planar CMOS devices.This indicates that the SET mechanism becomes more complicated during the FinFET process.Therefore,more effective SET hardening methods should be investigated for FinFET.展开更多
The failure mechanisms and structural damage of SiC MOSFETs induced by heavy ion irradiation were demonstrated.The findings reveal three degradation modes,depending on the drain voltage.At a relatively low voltage,the...The failure mechanisms and structural damage of SiC MOSFETs induced by heavy ion irradiation were demonstrated.The findings reveal three degradation modes,depending on the drain voltage.At a relatively low voltage,the damage is triggered by the formation and activation of gate latent damage(LDs),with damage concentrated in the gate oxide.The second degradation mode involves permanent leakage current degradation,with damage progressively transitioning from the oxide to the SiC material as the drain voltage escalates.Ultimately,the device undergoes catastrophic burnout above certain voltages,characterized by the lattice temperature reaching the sublimation point of SiC,resulting in surface cavity and complete structural destruction.This paper presents a comprehensive investigation of SiC MOSFETs under heavy ion exposure,providing radiation resistance methods of SiC-based devices for aerospace applications.展开更多
In this study,with the aim of achieving a high signal-to-noise ratio(SNR)in an electron-bombarded complementary metal-oxide-semiconductor(EBCMOS)imaging chip,we analyzed the sources of noise using principles from low-...In this study,with the aim of achieving a high signal-to-noise ratio(SNR)in an electron-bombarded complementary metal-oxide-semiconductor(EBCMOS)imaging chip,we analyzed the sources of noise using principles from low-light-level imaging and semiconductor theory,and established a physical computational model that relates the electron-multiplication layer to the noise characteristics of an EBCMOS chip in a uniformly doped structure with a P-type substrate.We conducted theoretical calculations to analyze the effects on noise characteristics of the passivation layer material and thickness,P-substrate doping concentration,P-substrate thickness,incident electron energy,and substrate temperature.By comparing the characteristics of pixel noise,dark current,multiplication electron numbers,and SNR under various structures,we simulated optimized structural parameters of the device.Our simulation results showed that the noise characteristics of the device could be optimized using an Al_(2)O_(3)passivation thickness of 15 nm and substrate temperature of 260 K,and by decreasing the doping concentration and thickness of the P-type substrate and increasing the incident electron energy.The optimized SNR were 252 e/e.And the substantial impact of dark current noise,primarily governed by interfacial defects,on the overall noise characteristics of the device.This research offers theoretical support to develop EBCMOS imaging chips with high gain and SNR.展开更多
β-Ga_(2)O_(3) MOS inverter should play a crucial role in β-Ga_(2)O_(3) electronic circuits. Enhancement-mode(E-mode) MOSFET was fabricated based on β-Ga_(2)O_(3) film grown by atomic layer deposition technology, an...β-Ga_(2)O_(3) MOS inverter should play a crucial role in β-Ga_(2)O_(3) electronic circuits. Enhancement-mode(E-mode) MOSFET was fabricated based on β-Ga_(2)O_(3) film grown by atomic layer deposition technology, and the β-Ga_(2)O_(3) inverter was further monolithically integrated on this basis. The β-Ga_(2)O_(3) n MOSFET exhibits excellent electrical characteristics with an on/off current ratio reaching 10^(5). The logic inverter shows outstanding voltage inversion characteristics under low-frequency from 1 to 400 Hz operation. As the frequency continues to increase to 10 K, the reverse characteristic becomes worse due to parasitic capacitance induced by processes, and the difference between the highest and lowest values of VOUT has an exponential decay relationship with the frequency. This paper provides the practice for the development of β-Ga_(2)O_(3)-based circuits.展开更多
Neuromorphic devices have garnered significant attention as potential building blocks for energy-efficient hardware systems owing to their capacity to emulate the computational efficiency of the brain.In this regard,r...Neuromorphic devices have garnered significant attention as potential building blocks for energy-efficient hardware systems owing to their capacity to emulate the computational efficiency of the brain.In this regard,reservoir computing(RC)framework,which leverages straightforward training methods and efficient temporal signal processing,has emerged as a promising scheme.While various physical reservoir devices,including ferroelectric,optoelectronic,and memristor-based systems,have been demonstrated,many still face challenges related to compatibility with mainstream complementary metal oxide semiconductor(CMOS)integration processes.This study introduced a silicon-based schottky barrier metal-oxide-semiconductor field effect transistor(SB-MOSFET),which was fabricated under low thermal budget and compatible with back-end-of-line(BEOL).The device demonstrated short-term memory characteristics,facilitated by the modulation of schottky barriers and charge trapping.Utilizing these characteristics,a RC system for temporal data processing was constructed,and its performance was validated in a 5×4 digital classification task,achieving an accuracy exceeding 98%after 50 training epochs.Furthermore,the system successfully processed temporal signal in waveform classification and prediction tasks using time-division multiplexing.Overall,the SB-MOSFET's high compatibility with CMOS technology provides substantial advantages for large-scale integration,enabling the development of energy-efficient reservoir computing hardware.展开更多
基金supported by the Natural Science Foundation of Guangdong Province,China (No.2025A1515011654)the National Natural Science Foundation of China (No.22090053)+3 种基金the Fundamental Research Funds for National Universities,China University of Geosciences (Wuhan)support from the program of China Scholarships Council (No.202406410155)Young Elite Scientists Sponsorship Program by CAST-Doctoral Student Special Plansupport from the S&T Special Program of Huzhou (No.2024GZ07)。
文摘Field-effect nanofluidic transistors(FENTs),biomimicking the structure and functionality of neuron,act as biological transistors with the ability to gate switching responses to external stimuli.The switching ratio has been verified to evaluate the performance of FENTs,but until recently,the response time,another crucial indicator,has been ignored.Employing finite-element method,we investigated the relationship among gate charge,switching ratio and response time by divisionally manipulating gate charge,including entrance surface and the surface of confinement space,for ion transport to optimize switching capability.The dual-split gate charge on FENTs exhibits synergistic effect on switching response.Based on the two regional gate charge on FENTs,multivalence ions in lower concentration,high aspect ratio and single channel show higher switching ratio but longer response time compared to monovalent ions.The findings highlight the necessity of balancing these two signals in FENTs and offer insights for optimizing their design and expanding applications to dual-signal-detection iontronics.
基金supported in part by National R&D Program for Major Research Instruments of China(No.62027814)。
文摘This study focuses on a 60 V trench MOSFET device designed for operation in space radiation environments.By increasing the bulk region concentration and placing the etched gate trench after the P+implantation process,we successfully reduced the threshold voltage shift from 6.5 to 2.2 V under a total dose of 400 krad(Si)^(60)Co,allowing the device to operate normally.Structurally,by embedding the source metal in the active and terminal regions,the device demonstrated current degradation without experiencing single-event burnout when subjected to a drain voltage of 60 V and a linear energy transfer value of 75.4 MeV·cm^(2)∕mg from tantalum-ion incidence.TCAD simulations verified that the embedded source metal effectively suppressed parasitic transistor conduction and eliminated the base-region expansion effect,thereby lowering the maximum temperature from 8000 to 1400 K.The irradiation effects of the embedded source metal in the terminal region were also investigated,which can improve the reverse recovery and ensure that the terminal metal does not melt prematurely,thereby significantly enhancing the radiation hardness of the device.
基金supported by Natural Science Foundation of China(Nos.62174180 and 62304258)National Key R&D Program of China(No.2023YFA1609000)。
文摘This paper quantitatively discusses the influence of well contact on single-event transient(SET)in sub-20 nm FinFET by two-photon absorption(TPA)pulse laser.Two groups of inverter chains were designed to investigate the impact of well contact distance on the FinFET process.The experimental results show that the SET pulse width has a bimodal symmetric distribution,which is different from that of a bulk planar CMOS device.To investigate the detailed mechanism of the phenomenon,a high-precision FinFET TCAD model was established,in which both Id-Vd and Id-Vg errors were less than 10%compared to the SPICE model provided by the commercial process.TCAD simulation under heavy ion injection showed the mechanism of the abnormal phenomenon,where the well contact plays a major role in charge collection at the near-well contact distance,while the source plays a major role at the far distance.This phenomenon is completely different from that of planar CMOS devices.This indicates that the SET mechanism becomes more complicated during the FinFET process.Therefore,more effective SET hardening methods should be investigated for FinFET.
基金Project supported by the National Key Research and Development Program of China(Grant No.2023YFA1609000)the National Natural Science Foundation of China(Grant Nos.U2341222,U2441248,12275061,and 12075069)。
文摘The failure mechanisms and structural damage of SiC MOSFETs induced by heavy ion irradiation were demonstrated.The findings reveal three degradation modes,depending on the drain voltage.At a relatively low voltage,the damage is triggered by the formation and activation of gate latent damage(LDs),with damage concentrated in the gate oxide.The second degradation mode involves permanent leakage current degradation,with damage progressively transitioning from the oxide to the SiC material as the drain voltage escalates.Ultimately,the device undergoes catastrophic burnout above certain voltages,characterized by the lattice temperature reaching the sublimation point of SiC,resulting in surface cavity and complete structural destruction.This paper presents a comprehensive investigation of SiC MOSFETs under heavy ion exposure,providing radiation resistance methods of SiC-based devices for aerospace applications.
文摘In this study,with the aim of achieving a high signal-to-noise ratio(SNR)in an electron-bombarded complementary metal-oxide-semiconductor(EBCMOS)imaging chip,we analyzed the sources of noise using principles from low-light-level imaging and semiconductor theory,and established a physical computational model that relates the electron-multiplication layer to the noise characteristics of an EBCMOS chip in a uniformly doped structure with a P-type substrate.We conducted theoretical calculations to analyze the effects on noise characteristics of the passivation layer material and thickness,P-substrate doping concentration,P-substrate thickness,incident electron energy,and substrate temperature.By comparing the characteristics of pixel noise,dark current,multiplication electron numbers,and SNR under various structures,we simulated optimized structural parameters of the device.Our simulation results showed that the noise characteristics of the device could be optimized using an Al_(2)O_(3)passivation thickness of 15 nm and substrate temperature of 260 K,and by decreasing the doping concentration and thickness of the P-type substrate and increasing the incident electron energy.The optimized SNR were 252 e/e.And the substantial impact of dark current noise,primarily governed by interfacial defects,on the overall noise characteristics of the device.This research offers theoretical support to develop EBCMOS imaging chips with high gain and SNR.
基金supported by Natural Science Basic Research Program of Shaanxi Province of China (No. 2023-JC-YB-574)National Natural Science Foundation of China (No. 62304178)。
文摘β-Ga_(2)O_(3) MOS inverter should play a crucial role in β-Ga_(2)O_(3) electronic circuits. Enhancement-mode(E-mode) MOSFET was fabricated based on β-Ga_(2)O_(3) film grown by atomic layer deposition technology, and the β-Ga_(2)O_(3) inverter was further monolithically integrated on this basis. The β-Ga_(2)O_(3) n MOSFET exhibits excellent electrical characteristics with an on/off current ratio reaching 10^(5). The logic inverter shows outstanding voltage inversion characteristics under low-frequency from 1 to 400 Hz operation. As the frequency continues to increase to 10 K, the reverse characteristic becomes worse due to parasitic capacitance induced by processes, and the difference between the highest and lowest values of VOUT has an exponential decay relationship with the frequency. This paper provides the practice for the development of β-Ga_(2)O_(3)-based circuits.
基金supported in part by the Chinese Academy of Sciences(No.XDA0330302)NSFC program(No.22127901)。
文摘Neuromorphic devices have garnered significant attention as potential building blocks for energy-efficient hardware systems owing to their capacity to emulate the computational efficiency of the brain.In this regard,reservoir computing(RC)framework,which leverages straightforward training methods and efficient temporal signal processing,has emerged as a promising scheme.While various physical reservoir devices,including ferroelectric,optoelectronic,and memristor-based systems,have been demonstrated,many still face challenges related to compatibility with mainstream complementary metal oxide semiconductor(CMOS)integration processes.This study introduced a silicon-based schottky barrier metal-oxide-semiconductor field effect transistor(SB-MOSFET),which was fabricated under low thermal budget and compatible with back-end-of-line(BEOL).The device demonstrated short-term memory characteristics,facilitated by the modulation of schottky barriers and charge trapping.Utilizing these characteristics,a RC system for temporal data processing was constructed,and its performance was validated in a 5×4 digital classification task,achieving an accuracy exceeding 98%after 50 training epochs.Furthermore,the system successfully processed temporal signal in waveform classification and prediction tasks using time-division multiplexing.Overall,the SB-MOSFET's high compatibility with CMOS technology provides substantial advantages for large-scale integration,enabling the development of energy-efficient reservoir computing hardware.
