In this paper,we present a novel first-order digitalΣΔconverter tailored for digital-to-analog applications,focusing on achieving both high yield and reduced silicon estate.Our approach incorporates a substantial le...In this paper,we present a novel first-order digitalΣΔconverter tailored for digital-to-analog applications,focusing on achieving both high yield and reduced silicon estate.Our approach incorporates a substantial level of dithering noise into the input signal,strategically aimed at mitigating the spurious frequencies commonly encountered in such converters.Validation of our design is performed through simulations using a high-level simulator specialized in mixed-signal circuit analysis.The results underscore the enhanced performance of our circuit,especially in reducing spurious frequencies,highlighting its efficiency and effectiveness.The final circuit exhibits an effective number of bits of 13.展开更多
MOS bulk transistor is reaching its limits： sub-threshold slope （SS）, drain induced barrier lowering （DIBL）, threshold voltage （VT） and VDD scaling slowing down, more power dissipation, less speed gain, less ac...MOS bulk transistor is reaching its limits： sub-threshold slope （SS）, drain induced barrier lowering （DIBL）, threshold voltage （VT） and VDD scaling slowing down, more power dissipation, less speed gain, less accuracy, variability and reliability issues. Fully depleted devices are mandatory to continue the technology roadmap. FDSOI technology relies on a thin layer of silicon that is over a buried oxide （BOx）. Called ultra thin body and buried oxide （UTBB） transistor, FDSOI transistors correspond to a simple evolution from conventional MOS bulk transistor. The capability to bias the back-gate allows us to implement calibration techniques without adding transistors in critical blocks. We have illustrated this technique on a very low power voltage-controlled oscillator （VCO） based on a ring oscillator （RO） designed in 28 nm FDSOI technology. Despite the fact that such VCO topology exhibits a larger phase noise, this design will address aggressively the size and power consumption reduction. Indeed we are using the efficient back-gate biasing offered by the FDSOI MOS transistor to compensate the mismatches between the different inverters of the ring oscillator to decrease jitter and phase noise. We will present the reasons which led us to use the FDSOI technology to reach the specifications of this PLL. The VCRO exhibits a 0.8 mW power consumption, with a phase noise about -94 dBc/Hz@l MHz.展开更多
文摘In this paper,we present a novel first-order digitalΣΔconverter tailored for digital-to-analog applications,focusing on achieving both high yield and reduced silicon estate.Our approach incorporates a substantial level of dithering noise into the input signal,strategically aimed at mitigating the spurious frequencies commonly encountered in such converters.Validation of our design is performed through simulations using a high-level simulator specialized in mixed-signal circuit analysis.The results underscore the enhanced performance of our circuit,especially in reducing spurious frequencies,highlighting its efficiency and effectiveness.The final circuit exhibits an effective number of bits of 13.
文摘MOS bulk transistor is reaching its limits： sub-threshold slope （SS）, drain induced barrier lowering （DIBL）, threshold voltage （VT） and VDD scaling slowing down, more power dissipation, less speed gain, less accuracy, variability and reliability issues. Fully depleted devices are mandatory to continue the technology roadmap. FDSOI technology relies on a thin layer of silicon that is over a buried oxide （BOx）. Called ultra thin body and buried oxide （UTBB） transistor, FDSOI transistors correspond to a simple evolution from conventional MOS bulk transistor. The capability to bias the back-gate allows us to implement calibration techniques without adding transistors in critical blocks. We have illustrated this technique on a very low power voltage-controlled oscillator （VCO） based on a ring oscillator （RO） designed in 28 nm FDSOI technology. Despite the fact that such VCO topology exhibits a larger phase noise, this design will address aggressively the size and power consumption reduction. Indeed we are using the efficient back-gate biasing offered by the FDSOI MOS transistor to compensate the mismatches between the different inverters of the ring oscillator to decrease jitter and phase noise. We will present the reasons which led us to use the FDSOI technology to reach the specifications of this PLL. The VCRO exhibits a 0.8 mW power consumption, with a phase noise about -94 dBc/Hz@l MHz.
