Time-varying frequency selective attenuation and colored noises are unfavorable characteristics of power line communication(PLC) channels of the low voltage networks.To overcome these disadvantages,a novel real-time d...Time-varying frequency selective attenuation and colored noises are unfavorable characteristics of power line communication(PLC) channels of the low voltage networks.To overcome these disadvantages,a novel real-time dynamic spectrum management(DSM) algorithm in orthogonal frequency division multiplexing(OFDM)-based high-speed narrow-band power line communication(HNPLC) systems is proposed,and the corresponding FPGA circuit is designed and realized.Performance of the proposed DSM is validated with a large amount of network experiments under practical PLC circumstance.As the noise in each narrow subcarrier is approximately Gaussian,the proposed DSM adopts the BER/SER expression formulized via the AWGN channel to provide a handy and universal strategy for power allocation.The real-time requirement is guaranteed by choosing subcarriers in group and employing the same modulation scheme within each transmission.These measures are suitable for any modulation scheme no matter the system criterion is to maximize data rate or minimize power/BER.Algorithm design and hardware implementation of the proposed DSM are given with some flexible and efficient conversions.The DSM circuit is carried out with Xilinx KC705.Simulation and practical experiments validate that the proposed real-time DSM significantly improves system performance.展开更多
基金Supported by the Tsinghua University International Science and Technology Cooperation Project(No.20133000197,20123000148)
文摘Time-varying frequency selective attenuation and colored noises are unfavorable characteristics of power line communication(PLC) channels of the low voltage networks.To overcome these disadvantages,a novel real-time dynamic spectrum management(DSM) algorithm in orthogonal frequency division multiplexing(OFDM)-based high-speed narrow-band power line communication(HNPLC) systems is proposed,and the corresponding FPGA circuit is designed and realized.Performance of the proposed DSM is validated with a large amount of network experiments under practical PLC circumstance.As the noise in each narrow subcarrier is approximately Gaussian,the proposed DSM adopts the BER/SER expression formulized via the AWGN channel to provide a handy and universal strategy for power allocation.The real-time requirement is guaranteed by choosing subcarriers in group and employing the same modulation scheme within each transmission.These measures are suitable for any modulation scheme no matter the system criterion is to maximize data rate or minimize power/BER.Algorithm design and hardware implementation of the proposed DSM are given with some flexible and efficient conversions.The DSM circuit is carried out with Xilinx KC705.Simulation and practical experiments validate that the proposed real-time DSM significantly improves system performance.
