A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-fo...A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-forward equal-izer(FFE)is employed in the quarter-rate transmitter(TX).The half-rate receiver(RX)incorporates a continuous-time linear equal-izer(CTLE),a 3-stage high-speed slicer with multi-clock-phase sampling,and a clock and data recovery(CDR).The experimen-tal results show that the TRx operates at a maximum speed of 56 Gb/s with chip-on board(COB)assembly.The 28 Gb/s NRZ eye diagram shows a far-end vertical eye opening of 210 mV with an output amplitude of 351 mV single-ended and the 56 Gb/s PAM-4 eye diagram exhibits far-end eye opening of 33 mV(upper-eye),31 mV(mid-eye),and 28 mV(lower-eye)with an output amplitude of 353 mV single-ended.The recovered 14 GHz clock from the RX exhibits random jitter(RJ)of 469 fs and deterministic jitter(DJ)of 8.76 ps.The 875 Mb/s de-multiplexed data features 593 ps horizontal eye opening with 32.02 ps RJ,at bit-error rate(BER)of 10-5(0.53 UI).The power dissipation of TX and RX are 125 and 181.4 mW,respectively,from a 0.9-V sup-ply.展开更多
This Special Topic of the Journal of Semiconductors(JoS)features expanded versions of key articles presented at the 2023 IEEE International Conference on Integrated Circuits Technologies and Applications(ICTA),which w...This Special Topic of the Journal of Semiconductors(JoS)features expanded versions of key articles presented at the 2023 IEEE International Conference on Integrated Circuits Technologies and Applications(ICTA),which was held in Hefei,Anhui,China,from October 27 to 29,2023.IEEE ICTA is an IEEE flagship conference in the field of integrated circuits(IC)in China,which provides a communication platform for sharing the state-of-the-art techniques from experts in the field of ICs.Among the 93 papers presented at ICTA 2023,the Technical Program Committee and the Award Committee have selected 4 high-quality articles to recommend to the Special Topic of JoS,covering a wide range of technical fields,including one paper on RF ICs,two papers on Analog ICs and one paper on Wireline ICs.展开更多
This paper presents a 130 GBaud four-to-one analog multiplexer(AMUX)with four-level pulse-amplitude modulation(PAM-4)in a 130-nm SiGe BiCMOS process.The architecture comprises two stages of the two-to-one AMUX.The fou...This paper presents a 130 GBaud four-to-one analog multiplexer(AMUX)with four-level pulse-amplitude modulation(PAM-4)in a 130-nm SiGe BiCMOS process.The architecture comprises two stages of the two-to-one AMUX.The four quarter-rate signals are fed into the first-stage AMUX circuit after equalization by continuous-time linear equalizers(CTLE)to produce two-way half-rate signals through time interleaving.The AMUX core circuit of the second stage is based on the Gilbert cell.Compared to the conventional sampling method where the clock signal is centered within 1UI of the data signal,the secondstage AMUX in this design aligns the rising edge of the clock signal with the transition edge of the data signal during sampling.This approach avoids the idle dummy branches in the conventional design,thereby significantly improving the energy efficiency.The AMUX generates two full-rate data signals spaced by 1-UI for subsequent feed-forward equalization(FFE).A two-tap FFE is designed with the transconductance(Gm)cell to compensate for the channel loss.As for the clock chain,the half-rate clock is provided by an external high speed clock source.It will pass through a voltage-controlled delay line(VCDL)to regulate the timing relationship between the clock and data signals in the second stage.And the two-way quarter-rate clocks in quadrature phases need to be generated from the half-rate clock for the two AMUXs in the first stage.Finally,a 130 GBaud PAM-4 signal is generated with a power consumption of 1 W.展开更多
This Special Issue is dedicated to the selected papers from the 2023 IEEE International Conference on Integrated Circuits Technologies and Applications(ICTA),held in Hefei,Anhui,China,from October 27 to 29,2023.ICTA i...This Special Issue is dedicated to the selected papers from the 2023 IEEE International Conference on Integrated Circuits Technologies and Applications(ICTA),held in Hefei,Anhui,China,from October 27 to 29,2023.ICTA is an IEEE flagship conference in the field of integrated circuits(ICs)in China,providing a platform for the presentation and exchange of the latest technical achievements and fostering cross-discipline collaboration in IC designs,technologies,and applications within the rapidly evolving technical community.展开更多
基金supported by National Natural Science Foundation of China under Grant 62174132the Fundamental Research Funds for Central Universities under Grant xzy022022060.
文摘A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-forward equal-izer(FFE)is employed in the quarter-rate transmitter(TX).The half-rate receiver(RX)incorporates a continuous-time linear equal-izer(CTLE),a 3-stage high-speed slicer with multi-clock-phase sampling,and a clock and data recovery(CDR).The experimen-tal results show that the TRx operates at a maximum speed of 56 Gb/s with chip-on board(COB)assembly.The 28 Gb/s NRZ eye diagram shows a far-end vertical eye opening of 210 mV with an output amplitude of 351 mV single-ended and the 56 Gb/s PAM-4 eye diagram exhibits far-end eye opening of 33 mV(upper-eye),31 mV(mid-eye),and 28 mV(lower-eye)with an output amplitude of 353 mV single-ended.The recovered 14 GHz clock from the RX exhibits random jitter(RJ)of 469 fs and deterministic jitter(DJ)of 8.76 ps.The 875 Mb/s de-multiplexed data features 593 ps horizontal eye opening with 32.02 ps RJ,at bit-error rate(BER)of 10-5(0.53 UI).The power dissipation of TX and RX are 125 and 181.4 mW,respectively,from a 0.9-V sup-ply.
文摘This Special Topic of the Journal of Semiconductors(JoS)features expanded versions of key articles presented at the 2023 IEEE International Conference on Integrated Circuits Technologies and Applications(ICTA),which was held in Hefei,Anhui,China,from October 27 to 29,2023.IEEE ICTA is an IEEE flagship conference in the field of integrated circuits(IC)in China,which provides a communication platform for sharing the state-of-the-art techniques from experts in the field of ICs.Among the 93 papers presented at ICTA 2023,the Technical Program Committee and the Award Committee have selected 4 high-quality articles to recommend to the Special Topic of JoS,covering a wide range of technical fields,including one paper on RF ICs,two papers on Analog ICs and one paper on Wireline ICs.
基金the National Natural Science Foundation of China under Grant 62174132.
文摘This paper presents a 130 GBaud four-to-one analog multiplexer(AMUX)with four-level pulse-amplitude modulation(PAM-4)in a 130-nm SiGe BiCMOS process.The architecture comprises two stages of the two-to-one AMUX.The four quarter-rate signals are fed into the first-stage AMUX circuit after equalization by continuous-time linear equalizers(CTLE)to produce two-way half-rate signals through time interleaving.The AMUX core circuit of the second stage is based on the Gilbert cell.Compared to the conventional sampling method where the clock signal is centered within 1UI of the data signal,the secondstage AMUX in this design aligns the rising edge of the clock signal with the transition edge of the data signal during sampling.This approach avoids the idle dummy branches in the conventional design,thereby significantly improving the energy efficiency.The AMUX generates two full-rate data signals spaced by 1-UI for subsequent feed-forward equalization(FFE).A two-tap FFE is designed with the transconductance(Gm)cell to compensate for the channel loss.As for the clock chain,the half-rate clock is provided by an external high speed clock source.It will pass through a voltage-controlled delay line(VCDL)to regulate the timing relationship between the clock and data signals in the second stage.And the two-way quarter-rate clocks in quadrature phases need to be generated from the half-rate clock for the two AMUXs in the first stage.Finally,a 130 GBaud PAM-4 signal is generated with a power consumption of 1 W.
文摘This Special Issue is dedicated to the selected papers from the 2023 IEEE International Conference on Integrated Circuits Technologies and Applications(ICTA),held in Hefei,Anhui,China,from October 27 to 29,2023.ICTA is an IEEE flagship conference in the field of integrated circuits(ICs)in China,providing a platform for the presentation and exchange of the latest technical achievements and fostering cross-discipline collaboration in IC designs,technologies,and applications within the rapidly evolving technical community.
