Based on the thermal network of the two-dimensional heterojunction bipolar transistors(HBTs) array, the thermal resistance matrix is presented, including the self-heating thermal resistance and thermal coupling resist...Based on the thermal network of the two-dimensional heterojunction bipolar transistors(HBTs) array, the thermal resistance matrix is presented, including the self-heating thermal resistance and thermal coupling resistance to describe the self-heating and thermal coupling effects, respectively.For HBT cells along the emitter length direction, the thermal coupling resistance is far smaller than the self-heating thermal resistance, and the peak junction temperature is mainly determined by the self-heating thermal resistance.However, the thermal coupling resistance is in the same order with the self-heating thermal resistance for HBT cells along the emitter width direction.Furthermore, the dependence of the thermal resistance matrix on cell spacing along the emitter length direction and cell spacing along the emitter width direction is also investigated, respectively.It is shown that the moderate increase of cell spacings along the emitter length direction and the emitter width direction could effectively lower the self-heating thermal resistance and thermal coupling resistance,and hence the peak junction temperature is decreased, which sheds light on adopting a two-dimensional non-uniform cell spacing layout to improve the uneven temperature distribution.By taking a 2 × 6 HBTs array for example, a twodimensional non-uniform cell spacing layout is designed, which can effectively lower the peak junction temperature and reduce the non-uniformity of the dissipated power.For the HBTs array with optimized layout, the high power-handling capability and thermal dissipation capability are kept when the bias voltage increases.展开更多
The impact of the variations of threshold voltage(V_(th))and hold voltage(V_(hold))of threshold switching(TS)selector in1 S1 R crossbar array is investigated.Based on ON/OFF state I–V curves measurements from a large...The impact of the variations of threshold voltage(V_(th))and hold voltage(V_(hold))of threshold switching(TS)selector in1 S1 R crossbar array is investigated.Based on ON/OFF state I–V curves measurements from a large number of Ag-filament TS selectors,V_(th)and V_(hold)are extracted and their variations distribution expressions are obtained,which are then employed to evaluate the impact on read process and write process in 32×321 S1 R crossbar array under different bias schemes.The results indicate that V_(th)and V_(hold)variations of TS selector can lead to degradation of 1 S1 R array performance parameters,such as minimum read/write voltage,bit error rate(BER),and power consumption.For the read process,a small V_(hold)variation not only results in the minimum read voltage increasing but it also leads to serious degradation of BER.As the standard deviation of V_(hold)and V_(th)increases,the BER and the power consumption of 1 S1 R crossbar array under 1/2 bias,1/3 bias,and floating scheme degrade,and the case under 1/2 bias tends to be more serious compared with other two schemes.For the write process,the minimum write voltage also increases with the variation of V_(hold)from small to large value.A slight increase of V_(th)standard deviation not only decreases write power efficiency markedly but also increases write power consumption.These results have reference significance to understand the voltage variation impacts and design of selector properly.展开更多
The effects of buried oxide（BOX） layer on the capacitance of SiGe heterojunction photo-transistor（HPT）,including the collector-substrate capacitance,the base-collector capacitance,and the base-emitter capacitance,...The effects of buried oxide（BOX） layer on the capacitance of SiGe heterojunction photo-transistor（HPT）,including the collector-substrate capacitance,the base-collector capacitance,and the base-emitter capacitance,are studied by using a silicon-on-insulator（SOI） substrate as compared with the devices on native Si substrates.By introducing the BOX layer into Si-based SiGe HPT,the maximum photo-characteristic frequency ft,0 p.of SO1-based SiGe HPT reaches up to 24.51 GHz,which is 1.5 times higher than the value obtained from Si-based SiGe HPT.In addition,the maximum optical cut-off frequency fβ,opt,namely its 3-dB bandwidth,reaches up to 1.13 GHz,improved by 1.18 times.However,with the increase of optical power or collector current,this improvement on the frequency characteristic from BOX layer becomes less dominant as confirmed by reducing the 3-dB bandwidth of SOI-based SiGe HPT which approaches to the 3-dB bandwidth of Si-based SiGe HPT at higher injection conditions.展开更多
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61006059 and 61774012)Beijing Municipal Natural Science Foundation,China(Grant No.4143059)+3 种基金Beijing Municipal Education Committee,China(Grant No.KM201710005027)Postdoctoral Science Foundation of Beijing,China(Grant No.2015ZZ-11)China Postdoctoral Science Foundation(Grant No.2015M580951)Scientific Research Foundation Project of Beijing Future Chip Technology Innovation Center,China(Grant No.KYJJ2016008)
文摘Based on the thermal network of the two-dimensional heterojunction bipolar transistors(HBTs) array, the thermal resistance matrix is presented, including the self-heating thermal resistance and thermal coupling resistance to describe the self-heating and thermal coupling effects, respectively.For HBT cells along the emitter length direction, the thermal coupling resistance is far smaller than the self-heating thermal resistance, and the peak junction temperature is mainly determined by the self-heating thermal resistance.However, the thermal coupling resistance is in the same order with the self-heating thermal resistance for HBT cells along the emitter width direction.Furthermore, the dependence of the thermal resistance matrix on cell spacing along the emitter length direction and cell spacing along the emitter width direction is also investigated, respectively.It is shown that the moderate increase of cell spacings along the emitter length direction and the emitter width direction could effectively lower the self-heating thermal resistance and thermal coupling resistance,and hence the peak junction temperature is decreased, which sheds light on adopting a two-dimensional non-uniform cell spacing layout to improve the uneven temperature distribution.By taking a 2 × 6 HBTs array for example, a twodimensional non-uniform cell spacing layout is designed, which can effectively lower the peak junction temperature and reduce the non-uniformity of the dissipated power.For the HBTs array with optimized layout, the high power-handling capability and thermal dissipation capability are kept when the bias voltage increases.
基金Project supported by the MOST of China(Grant No.2016YFA0201801)the Beijing Advanced Innovation Center for Future Chip(ICFC)+2 种基金Beijing Municipal Science and Technology Project(Grant No.D161100001716002)the National Natural Science Foundation of China(Grant Nos.61674089,61674087,61674092,61076115,and 61774012)the Research Fund from Beijing Innovation Center for Future Chip(Grant No.KYJJ2016008)
文摘The impact of the variations of threshold voltage(V_(th))and hold voltage(V_(hold))of threshold switching(TS)selector in1 S1 R crossbar array is investigated.Based on ON/OFF state I–V curves measurements from a large number of Ag-filament TS selectors,V_(th)and V_(hold)are extracted and their variations distribution expressions are obtained,which are then employed to evaluate the impact on read process and write process in 32×321 S1 R crossbar array under different bias schemes.The results indicate that V_(th)and V_(hold)variations of TS selector can lead to degradation of 1 S1 R array performance parameters,such as minimum read/write voltage,bit error rate(BER),and power consumption.For the read process,a small V_(hold)variation not only results in the minimum read voltage increasing but it also leads to serious degradation of BER.As the standard deviation of V_(hold)and V_(th)increases,the BER and the power consumption of 1 S1 R crossbar array under 1/2 bias,1/3 bias,and floating scheme degrade,and the case under 1/2 bias tends to be more serious compared with other two schemes.For the write process,the minimum write voltage also increases with the variation of V_(hold)from small to large value.A slight increase of V_(th)standard deviation not only decreases write power efficiency markedly but also increases write power consumption.These results have reference significance to understand the voltage variation impacts and design of selector properly.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61604106,61774012,and 61901010)the Beijing Future Chip Technology High Precision Innovation Center Research Fund,China(Grant No.KYJJ2016008)+1 种基金the Beijing Municipal Natural Science Foundation,China(Grant No.4192014)the Municipal Natural Science Foundation of Shangdong Province,China(Grant No.ZR2014FL025).
文摘The effects of buried oxide（BOX） layer on the capacitance of SiGe heterojunction photo-transistor（HPT）,including the collector-substrate capacitance,the base-collector capacitance,and the base-emitter capacitance,are studied by using a silicon-on-insulator（SOI） substrate as compared with the devices on native Si substrates.By introducing the BOX layer into Si-based SiGe HPT,the maximum photo-characteristic frequency ft,0 p.of SO1-based SiGe HPT reaches up to 24.51 GHz,which is 1.5 times higher than the value obtained from Si-based SiGe HPT.In addition,the maximum optical cut-off frequency fβ,opt,namely its 3-dB bandwidth,reaches up to 1.13 GHz,improved by 1.18 times.However,with the increase of optical power or collector current,this improvement on the frequency characteristic from BOX layer becomes less dominant as confirmed by reducing the 3-dB bandwidth of SOI-based SiGe HPT which approaches to the 3-dB bandwidth of Si-based SiGe HPT at higher injection conditions.
