Low-power designs are getting increased significance in numerous applications like high-performance computing and wireless communication due to the rise in power dissipation.Power dissipation of VLSI(very large scale ...Low-power designs are getting increased significance in numerous applications like high-performance computing and wireless communication due to the rise in power dissipation.Power dissipation of VLSI(very large scale integration)circuits in test mode is much higher than in the normal operation mode due to the high frequency of applied test patterns.Product lifetime,yield,reduced performance,and circuit damage will result from this additional power consumption in testing.Therefore,the main objective of today’s test applications is to minimize power dissipation by increasing the correlation of applied successive test vectors.Low-power test pattern generator(TPG)using LFSR(linear feedback shift register)and binary to the excess-4 converter and binary ripple counter is proposed.The test vectors generated by the TPG have a high correlation between successive test vectors,which leads to minimum switching.During the testing of benchmark circuits,the proposed method shows a significant reduction in dynamic power consumption concerning its peer works.展开更多
文摘Low-power designs are getting increased significance in numerous applications like high-performance computing and wireless communication due to the rise in power dissipation.Power dissipation of VLSI(very large scale integration)circuits in test mode is much higher than in the normal operation mode due to the high frequency of applied test patterns.Product lifetime,yield,reduced performance,and circuit damage will result from this additional power consumption in testing.Therefore,the main objective of today’s test applications is to minimize power dissipation by increasing the correlation of applied successive test vectors.Low-power test pattern generator(TPG)using LFSR(linear feedback shift register)and binary to the excess-4 converter and binary ripple counter is proposed.The test vectors generated by the TPG have a high correlation between successive test vectors,which leads to minimum switching.During the testing of benchmark circuits,the proposed method shows a significant reduction in dynamic power consumption concerning its peer works.
