The effects of atropine, diazepam and pralidoxime were studied for their ability to block the pathological lesions induced by sarin. Rats were exposed to an aerosol of sarin at a concentration of 51.2mg-m for 15 min f...The effects of atropine, diazepam and pralidoxime were studied for their ability to block the pathological lesions induced by sarin. Rats were exposed to an aerosol of sarin at a concentration of 51.2mg-m for 15 min following the pretreatment with one of the following combinations: atropine (10 mg/kg, i.m.) and diazepam (0.5 mg/kg, i.m.); atropine and pralidoxime (25 mg/kg, i.m.); diazepam and pralidoxime; atropine, diazepam and pralidoxime. Lung exposed to sarin aerosols revealed an increased cellular proliferation with progressive diffused interstitial thickening on the 4th day following exposure. On the 16th day, loss of alveolar space and consolidation of large areas of all lobes were observed. Sarin also caused damage to the respiratory bronchioles. All the therapy regime blocked the development of lung lesions in the descending orders: atropine, diazepam and pralidoxime, atropine and diazepam > diazepam and pralidoxime > atropine and pralidoxime. The result suggests that diazepam in combination with atropine and pralidoxime could be an effective drug combination regime for the lung lesions.展开更多
Cultivation of bay leaves （Cinnamomum tamalaNees ＆ Eberm） to fulfil household income needs is a long established practice in Udayapur district of Nepal. The practices adopted by farmers for bay leaf harvesting have...Cultivation of bay leaves （Cinnamomum tamalaNees ＆ Eberm） to fulfil household income needs is a long established practice in Udayapur district of Nepal. The practices adopted by farmers for bay leaf harvesting have not, however, been validated by scientific investigation for their sustainability. To investigate the impacts of harvesting on the yield of branch, leaves and biomass of leaves, a two-year research project was conducted in farm fields at Kopche village of Routa VDC in Udayapur district, Nepal. Four different harvesting treatments, the orien-tation and the order of branches were taken as independent variables to test their effects on number of branches, leaves and biomass of leaves. Orientation, harvesting treatments and order of branches had a significant effect on the number of branches, but not on the number of leaves or biomass （fresh and dry weight） of leaves in the year of harvest. Between two consecutive harvests there was no significant difference in the num-ber of branches, leaves or biomass. Lower two-thirds portion of the trees produced the largest number of leaves and branches of the fourth order in both years. Therefore, lower two-thirds portion of the trees were suitable for harvesting. Our findings support farmer experience that no change in productivity of leaves is observed when harvesting each year. For long term sustainability, harvesting should be conducted without debarking of trees or damage to branches. Our findings could be extrapolated to and tested in other areas with different access and user rights where the rota-tion for harvest is fixed or regulated without research evidence.展开更多
We analyze the energy performance of a complete adiabatic circuit/system including the Power Clock Generator （PCG） at the 90 nm CMOS technology node. The energy performance in terms of the conversion efficiency of t...We analyze the energy performance of a complete adiabatic circuit/system including the Power Clock Generator （PCG） at the 90 nm CMOS technology node. The energy performance in terms of the conversion efficiency of the PCG is extensively carried out under the variations of supply voltage, process comer and the driver transistor＇s width. We propose an energy-efficient singe cycle control circuit based on the two-stage comparator for the synchronous charge recovery sinusoidal power clock generator （PCG）. The proposed PCG is used to drive the 4-bit adiabatic Ripple Carry Adder （RCA） and their simulation results are compared with the adiabatic RCA driven by the reported PCG. We have also simulated the logically equivalent static CMOS RCA circuit to compare the energy saving of adiabatic and non-adiabatic logic circuits. In the clock frequency range from 25 MHz to 1GHz, the proposed PCG gives a maximum conversion efficiency of 56.48%. This research work shows how the design of an efficient PCG increases the energy saving of adiabatic logic.展开更多
The present paper analyzes the hold and read stability with temperature and aspect ratio variations. To reduce the power dissipation, one of the effective techniques is the supply voltage reduction. At this reduced su...The present paper analyzes the hold and read stability with temperature and aspect ratio variations. To reduce the power dissipation, one of the effective techniques is the supply voltage reduction. At this reduced supply voltage the data must be stable. So, the minimum voltage should be discovered which can also retain the data. This voltage is the data retention voltage（DRV）. The DRV for 6T SRAM cell is estimated and analyzed in this paper.The sensitivity analysis is performed for the DRV variation with the variation in the temperature and aspect ratio of the pull up and pull down transistors. Cadence Virtuoso is used for DRV analysis using 45 nm GPDK technology files. After this, the read stability analysis of 6T SRAM cell in terms of SRRV（supply read retention voltage） and WRRV（wordline read retention voltage） is carried out. Read stability in terms of RSNM can be discovered by accessing the internal storage nodes. But in the case of dense SRAM arrays instead of using internal storage nodes,the stability can be discovered by using direct bit line measurements with the help of SRRV and WRRV. SRRV is used to find the minimum supply voltage for which data can be retained during a read operation. Similarly, WRRV is used to find the boosted value of wordline voltage, for which data can be retained during read operation. The SRRV and WRRV values are then analyzed for different Cell Ratios. The results of SRRV and WRRV are then compared with the reported data for the validation of the accuracy of the results.展开更多
This paper delineates the effect of nonplanar structure of Fin FETs on noise performance. We demonstrate the thermal noise analytical model that has been inferred by taking into account the presence of an additional i...This paper delineates the effect of nonplanar structure of Fin FETs on noise performance. We demonstrate the thermal noise analytical model that has been inferred by taking into account the presence of an additional inverted region in the extended（underlap） S/D region due to finite gate electrode thickness. Noise investigation includes the effects of source drain resistances which become significant as channel length becomes shorter. In this paper, we evaluate the additional noise caused by three dimensional（3-D） structure of the single fin device and then extended analysis of the multi-fin and multi-fingers structure. The addition of fringe field increases its minimum noise figure and noise resistance of approximately 1 d B and 100Ω respectively and optimum admittance increases to 5.45 mΩ at 20 GHz for a device operating under saturation region. Hence, our transformed model plays a significant function in evaluation of accurate noise performance at circuit level.展开更多
A detailed investigation carried out, with the help of extensive simulations using the TCAD device simulator Sentaurus, with the aim of achieving an understanding of the effects of variations in gate and drain potenti...A detailed investigation carried out, with the help of extensive simulations using the TCAD device simulator Sentaurus, with the aim of achieving an understanding of the effects of variations in gate and drain potentials on the device characteristics of a silicon double-gate tunnel field effect transistor（Si-DG TFET） is reported in this paper. The investigation is mainly aimed at studying electrical properties such as the electric potential, the electron density, and the electron quasi-Fermi potential in a channel. From the simulation results, it is found that the electrical properties in the channel region of the DG TFET are different from those for a DG MOSFET. It is observed that the central channel potential of the DG TFET is not pinned to a fixed potential even after the threshold is passed（as in the case of the DG MOSFET）; instead, it initially increases and later on decreases with increasing gate voltage, and this is also the behavior exhibited by the surface potential of the device. However, the drain current always increases with the applied gate voltage. It is also observed that the electron quasi-Fermi potential（e QFP）decreases as the channel potential starts to decrease, and there are hiphops in the channel e QFP for higher applied drain voltages. The channel regime resistance is also observed for higher gate length, which has a great effect on the I–V characteristics of the DG TFET device. These channel regime electrical properties will be very useful for determining the tunneling current; thus these results may have further uses in developing analytical current models.展开更多
This paper presents an analytical model to study the scaling trends in energy recovery logic.The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology pa...This paper presents an analytical model to study the scaling trends in energy recovery logic.The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage,device threshold voltage and gate oxide thickness.The proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the nanoscale.This research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.展开更多
文摘The effects of atropine, diazepam and pralidoxime were studied for their ability to block the pathological lesions induced by sarin. Rats were exposed to an aerosol of sarin at a concentration of 51.2mg-m for 15 min following the pretreatment with one of the following combinations: atropine (10 mg/kg, i.m.) and diazepam (0.5 mg/kg, i.m.); atropine and pralidoxime (25 mg/kg, i.m.); diazepam and pralidoxime; atropine, diazepam and pralidoxime. Lung exposed to sarin aerosols revealed an increased cellular proliferation with progressive diffused interstitial thickening on the 4th day following exposure. On the 16th day, loss of alveolar space and consolidation of large areas of all lobes were observed. Sarin also caused damage to the respiratory bronchioles. All the therapy regime blocked the development of lung lesions in the descending orders: atropine, diazepam and pralidoxime, atropine and diazepam > diazepam and pralidoxime > atropine and pralidoxime. The result suggests that diazepam in combination with atropine and pralidoxime could be an effective drug combination regime for the lung lesions.
文摘Cultivation of bay leaves （Cinnamomum tamalaNees ＆ Eberm） to fulfil household income needs is a long established practice in Udayapur district of Nepal. The practices adopted by farmers for bay leaf harvesting have not, however, been validated by scientific investigation for their sustainability. To investigate the impacts of harvesting on the yield of branch, leaves and biomass of leaves, a two-year research project was conducted in farm fields at Kopche village of Routa VDC in Udayapur district, Nepal. Four different harvesting treatments, the orien-tation and the order of branches were taken as independent variables to test their effects on number of branches, leaves and biomass of leaves. Orientation, harvesting treatments and order of branches had a significant effect on the number of branches, but not on the number of leaves or biomass （fresh and dry weight） of leaves in the year of harvest. Between two consecutive harvests there was no significant difference in the num-ber of branches, leaves or biomass. Lower two-thirds portion of the trees produced the largest number of leaves and branches of the fourth order in both years. Therefore, lower two-thirds portion of the trees were suitable for harvesting. Our findings support farmer experience that no change in productivity of leaves is observed when harvesting each year. For long term sustainability, harvesting should be conducted without debarking of trees or damage to branches. Our findings could be extrapolated to and tested in other areas with different access and user rights where the rota-tion for harvest is fixed or regulated without research evidence.
基金Project supported by the Special Man-Power Development Programme in VLSI & Related Software,Phase-Ⅱ(SMDP-Ⅱ),Ministry of Information Technology,Government of Indiathe JUET,Guna(M.P.)
文摘We analyze the energy performance of a complete adiabatic circuit/system including the Power Clock Generator （PCG） at the 90 nm CMOS technology node. The energy performance in terms of the conversion efficiency of the PCG is extensively carried out under the variations of supply voltage, process comer and the driver transistor＇s width. We propose an energy-efficient singe cycle control circuit based on the two-stage comparator for the synchronous charge recovery sinusoidal power clock generator （PCG）. The proposed PCG is used to drive the 4-bit adiabatic Ripple Carry Adder （RCA） and their simulation results are compared with the adiabatic RCA driven by the reported PCG. We have also simulated the logically equivalent static CMOS RCA circuit to compare the energy saving of adiabatic and non-adiabatic logic circuits. In the clock frequency range from 25 MHz to 1GHz, the proposed PCG gives a maximum conversion efficiency of 56.48%. This research work shows how the design of an efficient PCG increases the energy saving of adiabatic logic.
文摘The present paper analyzes the hold and read stability with temperature and aspect ratio variations. To reduce the power dissipation, one of the effective techniques is the supply voltage reduction. At this reduced supply voltage the data must be stable. So, the minimum voltage should be discovered which can also retain the data. This voltage is the data retention voltage（DRV）. The DRV for 6T SRAM cell is estimated and analyzed in this paper.The sensitivity analysis is performed for the DRV variation with the variation in the temperature and aspect ratio of the pull up and pull down transistors. Cadence Virtuoso is used for DRV analysis using 45 nm GPDK technology files. After this, the read stability analysis of 6T SRAM cell in terms of SRRV（supply read retention voltage） and WRRV（wordline read retention voltage） is carried out. Read stability in terms of RSNM can be discovered by accessing the internal storage nodes. But in the case of dense SRAM arrays instead of using internal storage nodes,the stability can be discovered by using direct bit line measurements with the help of SRRV and WRRV. SRRV is used to find the minimum supply voltage for which data can be retained during a read operation. Similarly, WRRV is used to find the boosted value of wordline voltage, for which data can be retained during read operation. The SRRV and WRRV values are then analyzed for different Cell Ratios. The results of SRRV and WRRV are then compared with the reported data for the validation of the accuracy of the results.
基金Project supported in part by the All India Council for Technical Education(AICTE)
文摘This paper delineates the effect of nonplanar structure of Fin FETs on noise performance. We demonstrate the thermal noise analytical model that has been inferred by taking into account the presence of an additional inverted region in the extended（underlap） S/D region due to finite gate electrode thickness. Noise investigation includes the effects of source drain resistances which become significant as channel length becomes shorter. In this paper, we evaluate the additional noise caused by three dimensional（3-D） structure of the single fin device and then extended analysis of the multi-fin and multi-fingers structure. The addition of fringe field increases its minimum noise figure and noise resistance of approximately 1 d B and 100Ω respectively and optimum admittance increases to 5.45 mΩ at 20 GHz for a device operating under saturation region. Hence, our transformed model plays a significant function in evaluation of accurate noise performance at circuit level.
文摘A detailed investigation carried out, with the help of extensive simulations using the TCAD device simulator Sentaurus, with the aim of achieving an understanding of the effects of variations in gate and drain potentials on the device characteristics of a silicon double-gate tunnel field effect transistor（Si-DG TFET） is reported in this paper. The investigation is mainly aimed at studying electrical properties such as the electric potential, the electron density, and the electron quasi-Fermi potential in a channel. From the simulation results, it is found that the electrical properties in the channel region of the DG TFET are different from those for a DG MOSFET. It is observed that the central channel potential of the DG TFET is not pinned to a fixed potential even after the threshold is passed（as in the case of the DG MOSFET）; instead, it initially increases and later on decreases with increasing gate voltage, and this is also the behavior exhibited by the surface potential of the device. However, the drain current always increases with the applied gate voltage. It is also observed that the electron quasi-Fermi potential（e QFP）decreases as the channel potential starts to decrease, and there are hiphops in the channel e QFP for higher applied drain voltages. The channel regime resistance is also observed for higher gate length, which has a great effect on the I–V characteristics of the DG TFET device. These channel regime electrical properties will be very useful for determining the tunneling current; thus these results may have further uses in developing analytical current models.
基金supported by the Project SMDP-II,MCIT,Govt.of India
文摘This paper presents an analytical model to study the scaling trends in energy recovery logic.The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage,device threshold voltage and gate oxide thickness.The proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the nanoscale.This research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.
