期刊文献+
共找到1篇文章
< 1 >
每页显示 20 50 100
IMPROVEMENT IN PARAMETRIC AND RELIABILITY PERFORMANCE OF 90NM DUAL-DAMASCENE INTERCONNECTS USING AR+PUNCHTHRU PVD BARRIER PROCESS Reprinted with permission as presented at SEMICON China 2005
1
作者 N.Kumar s.chu +4 位作者 D.L.Diehl K.Maekawa K.Mori K.Kobayashi M.Yoneda 《集成电路应用》 2005年第9期43-49,共7页
As interconnects shrink beyond 90nm node, the presence of etch residues can createhigh via resistance and void nucleation during stress migration (SM) testing. Physical Ar+ preclean is effectivein removing residues, b... As interconnects shrink beyond 90nm node, the presence of etch residues can createhigh via resistance and void nucleation during stress migration (SM) testing. Physical Ar+ preclean is effectivein removing residues, but early SM failures have been seen due to Cu resputter from underlying trenches.Reactive preclean methods show promise in reducing CuOx and cleaning Si, N, F, C,O etch residues inpresence of H+, H* species. In this paper, reactive preclean and PVD PunchThru process (deposit-etch-deposit) is proposed as solution to conventional PVD.The PunchThru process reduces via resistance, improves SM and protects dual-damascene beveland unlanded vias from Cu diffusion by presence of thin Ta deposition step. In addition, the U-shaped interface,which minimizes electron crowding and localized heating effects, increases the mean time to failureby electromigration. Consistent, repeatable blanket film property and good parametric electrical test resultshave proven the production worthiness of this process. 展开更多
关键词 集成电路 芯片 制造工艺 封装技术
在线阅读 下载PDF
上一页 1 下一页 到第
使用帮助 返回顶部