As Moore’s Law comes to an end,the implementation of high-performance chips through transistor scaling has become increasingly challenging.To improve performance,increasing the chip area to integrate more transistors...As Moore’s Law comes to an end,the implementation of high-performance chips through transistor scaling has become increasingly challenging.To improve performance,increasing the chip area to integrate more transistors has become an essential approach.However,due to restrictions such as the maximum reticle area,cost,and manufacturing yield,the chip’s area cannot be continuously increased,and it encounters what is known as the“area-wall”.In this paper,we provide a detailed analysis of the area-wall and propose a practical solution,the Big Chip,as a novel chip form to continuously improve performance.We introduce a performance model for evaluating Big Chip and discuss its architecture.Finally,we derive the future development trends of the Big Chip.展开更多
Due to the waning of Moore’s Law,the conventional monolithic chip architectural design is confronting hurdles such as increasing die size and skyrocketing cost.In this post-Moore era,the integrated chip has emerged a...Due to the waning of Moore’s Law,the conventional monolithic chip architectural design is confronting hurdles such as increasing die size and skyrocketing cost.In this post-Moore era,the integrated chip has emerged as a pivotal technology,gaining substantial interest from both the academia and industry.Compared with monolithic chips,the chiplet-based integrated chips can significantly enhance system scalability,curtail costs,and accelerate design cycles.However,integrated chips introduce vast design spaces encompassing chiplets,inter-chiplet connections,and packaging parameters,thereby amplifying the complexity of the design process.This paper introduces the Optimal Decomposition-Combination Theory,a novel methodology to guide the decomposition and combination processes in integrated chip design.Furthermore,it offers a thorough examination of existing integrated chip design methodologies to showcase the application of this theory.展开更多
For decades,Moore’s Law[1],which predicted that the number of transistors on a chip would double every two years,has been a key driver of computing power growth.However,as transistor scaling approaches its physical l...For decades,Moore’s Law[1],which predicted that the number of transistors on a chip would double every two years,has been a key driver of computing power growth.However,as transistor scaling approaches its physical limits[2],challenges like heat dissipation,rising power density,and quantum effects are making it increasingly difficult to sustain this progress.In response,systems of integrated chips[3].展开更多
With the explosive growth of information, more and more organizations are deploying private cloud systems or renting public cloud systems to process big data. However, there is no existing benchmark suite for evaluati...With the explosive growth of information, more and more organizations are deploying private cloud systems or renting public cloud systems to process big data. However, there is no existing benchmark suite for evaluating cloud performance on the whole system level. To the best of our knowledge, this paper proposes the first benchmark suite CloudRank-D to benchmark and rank cloud computing sys- tems that are shared for running big data applications. We an- alyze the limitations of previous metrics, e.g., floating point operations, for evaluating a cloud computing system, and propose two simple metrics： data processed per second and data processed per Joule as two complementary metrics for evaluating cloud computing systems. We detail the design of CloudRank-D that considers representative applications, di- versity of data characteristics, and dynamic behaviors of both applications and system software platforms. Through experi- ments, we demonstrate the advantages of our proposed met- tics. In several case studies, we evaluate two small-scale de- ployments of cloud computing systems using CloudRank-D.展开更多
基金supported in part by the National Natural Science Foundation of China(61834006,62025404,62104229,62104230,61874124,62222411)in part by the Strategic Priority Research Program of Chinese Academy of Sciences(XDB44030300,XDB44020300)Zhejiang Lab under Grants 2021PC0AC01.
文摘As Moore’s Law comes to an end,the implementation of high-performance chips through transistor scaling has become increasingly challenging.To improve performance,increasing the chip area to integrate more transistors has become an essential approach.However,due to restrictions such as the maximum reticle area,cost,and manufacturing yield,the chip’s area cannot be continuously increased,and it encounters what is known as the“area-wall”.In this paper,we provide a detailed analysis of the area-wall and propose a practical solution,the Big Chip,as a novel chip form to continuously improve performance.We introduce a performance model for evaluating Big Chip and discuss its architecture.Finally,we derive the future development trends of the Big Chip.
基金supported in part by the National Natural Science Foundation of China(NSFC)under Grant 92373206,Grant 62222411,and Grant 62025404in part by the National Key Research and Development Program of China under Grant 2023YFB4404400.
文摘Due to the waning of Moore’s Law,the conventional monolithic chip architectural design is confronting hurdles such as increasing die size and skyrocketing cost.In this post-Moore era,the integrated chip has emerged as a pivotal technology,gaining substantial interest from both the academia and industry.Compared with monolithic chips,the chiplet-based integrated chips can significantly enhance system scalability,curtail costs,and accelerate design cycles.However,integrated chips introduce vast design spaces encompassing chiplets,inter-chiplet connections,and packaging parameters,thereby amplifying the complexity of the design process.This paper introduces the Optimal Decomposition-Combination Theory,a novel methodology to guide the decomposition and combination processes in integrated chip design.Furthermore,it offers a thorough examination of existing integrated chip design methodologies to showcase the application of this theory.
文摘For decades,Moore’s Law[1],which predicted that the number of transistors on a chip would double every two years,has been a key driver of computing power growth.However,as transistor scaling approaches its physical limits[2],challenges like heat dissipation,rising power density,and quantum effects are making it increasingly difficult to sustain this progress.In response,systems of integrated chips[3].
文摘With the explosive growth of information, more and more organizations are deploying private cloud systems or renting public cloud systems to process big data. However, there is no existing benchmark suite for evaluating cloud performance on the whole system level. To the best of our knowledge, this paper proposes the first benchmark suite CloudRank-D to benchmark and rank cloud computing sys- tems that are shared for running big data applications. We an- alyze the limitations of previous metrics, e.g., floating point operations, for evaluating a cloud computing system, and propose two simple metrics： data processed per second and data processed per Joule as two complementary metrics for evaluating cloud computing systems. We detail the design of CloudRank-D that considers representative applications, di- versity of data characteristics, and dynamic behaviors of both applications and system software platforms. Through experi- ments, we demonstrate the advantages of our proposed met- tics. In several case studies, we evaluate two small-scale de- ployments of cloud computing systems using CloudRank-D.
