Considerable research has considered the design of low-power and high-speed devices.Designing integrated circuits with low-power consumption is an important issue due to the rapid growth of high-speed devices.Embedded...Considerable research has considered the design of low-power and high-speed devices.Designing integrated circuits with low-power consumption is an important issue due to the rapid growth of high-speed devices.Embedded static random-access memory(SRAM)units are necessary components in fast mobile computing.Traditional SRAM cells are more energyconsuming and with lower performances.The major constraints in SRAM cells are their reliability and low power.The objectives of the proposed method are to provide a high read stability,low energy consumption,and better writing abilities.A transmission gate-based multi-threshold single-ended Schmitt trigger(ST)9T SRAM cell in a bit-interleaving structure without a write-back scheme is proposed.Herein,an ST inverter with a single bit-line design is used to attain the high read stability.A negative assist technique is applied to alter the trip voltage of the single-ended ST inverter.The multithreshold complementary metal oxide semiconductor(MTCMOS)technique is adopted to reduce the leakage power in the proposed single-ended TGST 9T SRAM cell.The proposed system uses a combination of standard and ST inverters,which results in a large read stability.Compared with the previous ST 9T,ST 11T,11T,10T,and 7T SRAM cells,the proposed cell is implemented in Cadence Virtuoso ADE with 45-nm CMOS technology and consumes 35.80%,42.09%,31.60%,12.54%,and 31.60%less energy for read operations and 73.59%,93.95%,92.76%,89.23%,and 85.78%less energy for write operations,respectively.展开更多
Advanced technology used for arithmetic computing application,comprises greater number of approximatemultipliers and approximate adders.Truncation and Rounding-based Scalable ApproximateMultiplier(TRSAM)distinguish a ...Advanced technology used for arithmetic computing application,comprises greater number of approximatemultipliers and approximate adders.Truncation and Rounding-based Scalable ApproximateMultiplier(TRSAM)distinguish a variety of modes based on height(h)and truncation(t)as TRSAM(h,t)in the architecture.This TRSAM operation produces higher absolute error in Least Significant Bit(LSB)data shift unit.A new scalable approximate multiplier approach that uses truncation and rounding TRSAM(3,7)is proposed to increase themultiplier accuracy.With the help of foremost one bit architecture,the proposed scalable approximate multiplier approach reduces the partial products.The proposed approximate TRSAM multiplier architecture gives better results in terms of area,delay,and power.The accuracy of 95.2%and the energy utilization of 24.6 nJ is observed in the proposed multiplier design.The proposed approach shows 0.11%,0.23%,and 0.24%less Mean Absolute Relative Error(MARE)when compared with the existing approach for the input of 8-bit,16-bit,and 32-bit respectively.It also shows 0.13%,0.19%,and 0.2%less Variance of Absolute Relative Error(VARE)when compared with the existing approach for the input of 8-bit,16-bit,and 32-bit respectively.The proposed approach is implemented with Field-Programmable Gate Array(FPGA)and shows the delay of 3.640,6.481,12.505,22.572,and 36.893 ns for the input of 8-bit,16-bit,32-bit,64-bit,and 128-bit respectively.The proposed approach is applied in digital filters designwhich shows the Peak-Signal-to-NoiseRatio(PSNR)of 25.05 dB and Structural Similarity Index Measure(SSIM)of 0.98 with 393 pJ energy consumptions when used in image application.The proposed approach is simulated with Xilinx and MATLAB and implemented with FPGA.展开更多
文摘Considerable research has considered the design of low-power and high-speed devices.Designing integrated circuits with low-power consumption is an important issue due to the rapid growth of high-speed devices.Embedded static random-access memory(SRAM)units are necessary components in fast mobile computing.Traditional SRAM cells are more energyconsuming and with lower performances.The major constraints in SRAM cells are their reliability and low power.The objectives of the proposed method are to provide a high read stability,low energy consumption,and better writing abilities.A transmission gate-based multi-threshold single-ended Schmitt trigger(ST)9T SRAM cell in a bit-interleaving structure without a write-back scheme is proposed.Herein,an ST inverter with a single bit-line design is used to attain the high read stability.A negative assist technique is applied to alter the trip voltage of the single-ended ST inverter.The multithreshold complementary metal oxide semiconductor(MTCMOS)technique is adopted to reduce the leakage power in the proposed single-ended TGST 9T SRAM cell.The proposed system uses a combination of standard and ST inverters,which results in a large read stability.Compared with the previous ST 9T,ST 11T,11T,10T,and 7T SRAM cells,the proposed cell is implemented in Cadence Virtuoso ADE with 45-nm CMOS technology and consumes 35.80%,42.09%,31.60%,12.54%,and 31.60%less energy for read operations and 73.59%,93.95%,92.76%,89.23%,and 85.78%less energy for write operations,respectively.
文摘Advanced technology used for arithmetic computing application,comprises greater number of approximatemultipliers and approximate adders.Truncation and Rounding-based Scalable ApproximateMultiplier(TRSAM)distinguish a variety of modes based on height(h)and truncation(t)as TRSAM(h,t)in the architecture.This TRSAM operation produces higher absolute error in Least Significant Bit(LSB)data shift unit.A new scalable approximate multiplier approach that uses truncation and rounding TRSAM(3,7)is proposed to increase themultiplier accuracy.With the help of foremost one bit architecture,the proposed scalable approximate multiplier approach reduces the partial products.The proposed approximate TRSAM multiplier architecture gives better results in terms of area,delay,and power.The accuracy of 95.2%and the energy utilization of 24.6 nJ is observed in the proposed multiplier design.The proposed approach shows 0.11%,0.23%,and 0.24%less Mean Absolute Relative Error(MARE)when compared with the existing approach for the input of 8-bit,16-bit,and 32-bit respectively.It also shows 0.13%,0.19%,and 0.2%less Variance of Absolute Relative Error(VARE)when compared with the existing approach for the input of 8-bit,16-bit,and 32-bit respectively.The proposed approach is implemented with Field-Programmable Gate Array(FPGA)and shows the delay of 3.640,6.481,12.505,22.572,and 36.893 ns for the input of 8-bit,16-bit,32-bit,64-bit,and 128-bit respectively.The proposed approach is applied in digital filters designwhich shows the Peak-Signal-to-NoiseRatio(PSNR)of 25.05 dB and Structural Similarity Index Measure(SSIM)of 0.98 with 393 pJ energy consumptions when used in image application.The proposed approach is simulated with Xilinx and MATLAB and implemented with FPGA.
