期刊文献+
共找到1篇文章
< 1 >
每页显示 20 50 100
Towards efficient deep neural network training by FPGA-based batch-level parallelism 被引量:4
1
作者 Cheng Luo man-kit sit +3 位作者 Hongxiang Fan Shuanglong Liu Wayne Luk Ce Guo 《Journal of Semiconductors》 EI CAS CSCD 2020年第2期51-62,共12页
Training deep neural networks(DNNs)requires a significant amount of time and resources to obtain acceptable results,which severely limits its deployment in resource-limited platforms.This paper proposes DarkFPGA,a nov... Training deep neural networks(DNNs)requires a significant amount of time and resources to obtain acceptable results,which severely limits its deployment in resource-limited platforms.This paper proposes DarkFPGA,a novel customizable framework to efficiently accelerate the entire DNN training on a single FPGA platform.First,we explore batch-level parallelism to enable efficient FPGA-based DNN training.Second,we devise a novel hardware architecture optimised by a batch-oriented data pattern and tiling techniques to effectively exploit parallelism.Moreover,an analytical model is developed to determine the optimal design parameters for the DarkFPGA accelerator with respect to a specific network specification and FPGA resource constraints.Our results show that the accelerator is able to perform about 10 times faster than CPU training and about a third of the energy consumption than GPU training using 8-bit integers for training VGG-like networks on the CIFAR dataset for the Maxeler MAX5 platform. 展开更多
关键词 deep neural network TRAINING FPGA batch-level parallelism
在线阅读 下载PDF
上一页 1 下一页 到第
使用帮助 返回顶部