Novel high speed energy efficient square root architecture has been reported in this paper. In this architecture, we have blended ancient Indian Vedic mathematics and Bakhshali mathematics to achieve a significant amo...Novel high speed energy efficient square root architecture has been reported in this paper. In this architecture, we have blended ancient Indian Vedic mathematics and Bakhshali mathematics to achieve a significant amount of accuracy in performing the square root operation. Basically, Vedic Duplex method and iterative division method reported in Bakhshali Manuscript have been utilized for that computation. The proposed technique has been compared with the well known Newton-Raphson’s (N-R) technique for square root computation. The algorithm has been implemented and tested using Modelsim simulator, and performance parameters such as the number of lookup tables, propagation delay and power consumption have been estimated using Xilinx ISE simulator. The functionality of the circuitry has been checked using Xilinx Virtex-5 FPGA board.展开更多
In this paper,focus has been given to design and implement signed binary subtraction in quantum logic.Since the type of operand may be positive or negative,therefore a novel algorithm has been developed to detect the ...In this paper,focus has been given to design and implement signed binary subtraction in quantum logic.Since the type of operand may be positive or negative,therefore a novel algorithm has been developed to detect the type of operand and as per the selection of the type of operands,separate design techniques have been developed to make the circuit compact and work very efficiently.Two separate methods have been shown in the paper to perform the signed subtraction.The results show promising for the second method in respect of ancillary input count and garbage output count but at the cost of quantum cost.展开更多
文摘Novel high speed energy efficient square root architecture has been reported in this paper. In this architecture, we have blended ancient Indian Vedic mathematics and Bakhshali mathematics to achieve a significant amount of accuracy in performing the square root operation. Basically, Vedic Duplex method and iterative division method reported in Bakhshali Manuscript have been utilized for that computation. The proposed technique has been compared with the well known Newton-Raphson’s (N-R) technique for square root computation. The algorithm has been implemented and tested using Modelsim simulator, and performance parameters such as the number of lookup tables, propagation delay and power consumption have been estimated using Xilinx ISE simulator. The functionality of the circuitry has been checked using Xilinx Virtex-5 FPGA board.
文摘In this paper,focus has been given to design and implement signed binary subtraction in quantum logic.Since the type of operand may be positive or negative,therefore a novel algorithm has been developed to detect the type of operand and as per the selection of the type of operands,separate design techniques have been developed to make the circuit compact and work very efficiently.Two separate methods have been shown in the paper to perform the signed subtraction.The results show promising for the second method in respect of ancillary input count and garbage output count but at the cost of quantum cost.
