This paper presents a 32 Gbps wireline transceiver that not only supports the JESD204 C standard but also maintains back-compatibility with JESD204B with minimal additional circuitry.Additionally,a pattern-filtered ph...This paper presents a 32 Gbps wireline transceiver that not only supports the JESD204 C standard but also maintains back-compatibility with JESD204B with minimal additional circuitry.Additionally,a pattern-filtered phase detector(PFPD)is proposed to circumvent the side effect of ambiguous sampling clock phase caused by loop-unrolled 1st post-cursor tap equalization scheme in the decision-feedback equalization(DFE).A 16 GHz external half-rate clock is injected into an on-chip injection-locked ring oscillator to distribute the 16 GHz clock for both the receiver and the transmitter.Multiple on-chip adaption engines and calibration loops are also added to assist the whole system work properly,such as tap weight and desired level adaption engine integrated into the decision-feedback equalizer,duty cycle distortion correction and IQ-mismatch correction.Fabricated in 28 nm CMOS process,the proposed transceiver demonstrates its ability to operate within a signaling range from 312.5 Mbps to 32 Gbps,achieving a BER below 10−12 over a 14.9 dB channel loss at Nyquist frequency.It occupies an aggregated area of 1.4 mm^(2)and consumes 203 mW at 32 Gbps,in which 50 mW for the transmitter(TX)and 153 mW for the receiver(RX),therefore end up achieving 6.34pJ/bit power efficiency at 32 Gbps.展开更多
基金supported by Beijing Municipal Science and Technology through Project Number Z221100007722024.
文摘This paper presents a 32 Gbps wireline transceiver that not only supports the JESD204 C standard but also maintains back-compatibility with JESD204B with minimal additional circuitry.Additionally,a pattern-filtered phase detector(PFPD)is proposed to circumvent the side effect of ambiguous sampling clock phase caused by loop-unrolled 1st post-cursor tap equalization scheme in the decision-feedback equalization(DFE).A 16 GHz external half-rate clock is injected into an on-chip injection-locked ring oscillator to distribute the 16 GHz clock for both the receiver and the transmitter.Multiple on-chip adaption engines and calibration loops are also added to assist the whole system work properly,such as tap weight and desired level adaption engine integrated into the decision-feedback equalizer,duty cycle distortion correction and IQ-mismatch correction.Fabricated in 28 nm CMOS process,the proposed transceiver demonstrates its ability to operate within a signaling range from 312.5 Mbps to 32 Gbps,achieving a BER below 10−12 over a 14.9 dB channel loss at Nyquist frequency.It occupies an aggregated area of 1.4 mm^(2)and consumes 203 mW at 32 Gbps,in which 50 mW for the transmitter(TX)and 153 mW for the receiver(RX),therefore end up achieving 6.34pJ/bit power efficiency at 32 Gbps.
