Purpose Improved resistive plate chambers(iRPCs)will be installed in the challenging forward region of the compact muon solenoid(CMS)during its Phase-2 upgrade.The design target of iRPC time resolution is 1.5 ns.It wi...Purpose Improved resistive plate chambers(iRPCs)will be installed in the challenging forward region of the compact muon solenoid(CMS)during its Phase-2 upgrade.The design target of iRPC time resolution is 1.5 ns.It will help the Level-1 trigger system distinguish the muons from high backgrounds and improve the trigger efficiency.Studying the time resolution after integrating the new backend electronics boards(BEB)is essential for ensuring timely performance.In this system,a time reference(Tref)signal is distributed by the BEB to several frontend electronics boards(FEB)to reset the time-to-digital converters(TDC).In the CMS experiment,the arrangement of the iRPC chambers and on-chamber FEBs is at different positions,resulting in varying Tref arrival times on the FEB side.This paper describes the measures taken to ensure the time resolution of the single path and adjust the time base for multi-paths.Method Unique designs were implemented in the chamber,FEB,and BEB to ensure a satisfactory time resolution.Tref adjustments for different paths were performed in bunch crossing steps(24.950 ns)in the BEB using shift registers.And the sub-bunch crossing adjustment steps were performed in the FEB using the TDC correction module.Finally,the arrival time differences of Tref on different FEBs were less than 1.25 ns after adjustment.Results The time resolution of the FEB–BEB system was observed to be 32 ps.The time resolution of the chamber FEB–BEB system was first measured and is 554 ps at an iRPC working point of 7200 V.In addition,the Tref arrival time differences of different paths were adjusted from−99.923(−90.113)ns to 0.073(−0.141)ns.Conclusion The test results revealed that the system time resolution and Tref adjustment performed by the BEB met the Phase-2 upgrade goals.展开更多
Purpose The Large Hadron Collider(LHC)at European Organization for Nuclear Research is planned to be upgraded to the high luminosity LHC.Increasing the luminosity makes muon triggering reliable and offline reconstructi...Purpose The Large Hadron Collider(LHC)at European Organization for Nuclear Research is planned to be upgraded to the high luminosity LHC.Increasing the luminosity makes muon triggering reliable and offline reconstruction very challenging.To enhance the redundancy of the Compact Muon Solenoid(CMS)Muon system and resolve the ambiguity of track reconstruction in the forward region,an improved Resistive Plate Chamber(iRPC)with excellent time resolution will be installed in the Phase-2 CMS upgrade.The iRPC will be equipped with Front-End Electronics(FEE),which can perform high-precision time measurements of signals from both ends of the strip.New Back-End Electronics(BEE)need to be researched and developed to provide sophisticated functionalities such as interacting with FEE with shared links for fast,slow control(SC)and data,in addition to trigger primitives(TPs)generation and data acquisition(DAQ).Method The BEE prototype uses a homemade hardware board compatible with the MTCA standard,the back-end board(BEB).BEE interacts with FEE via a bidirectional 4.8 Gbps optical paired-link that integrates clock,data,and control information.The clock and fast/slow control commands are distributed from BEB to the FEE via the downlink.The uplink is used for BEB to receive the time information of the iRPC’sfired strips and the responses to the fast/slow control commands.To have a pipelined detector data for clusterfinding operation,recover(DeMux)the time relationship of which is changed due to the transmission protocol for the continuous incoming MUXed data from FEE.Then at each bunch crossing(BX),clusteringfired strips that satisfy time and spatial constraints to generate TPs.Both incoming raw MUXed detector data and TPs in a time window and latency based on the trigger signal are read out to the DAQ system.Gigabit Ethernet(GbE)of SiTCP and commercial 10-GbE are used as link standards for SC and DAQ,respectively,for the BEB to interact with the server.Results The joint test results of the BEB with iRPC and Front-End Board(FEB)show a Bit Error Rate of the transmission links less than 1×10-16,a time resolution of the FEB Time-to-Digital Converter of 16 ps,and the resolution of the time difference between both ends of 160 ps which corresponding a spatial resolution of the iRPC of approximately 1.5 cm.Conclusion Test results showed the correctness and stable running of the BEB prototype,of which the functionalities fulfill the iRPC requirements.展开更多
Purpose To complement and ensure redundancy in the endcap muon system of the Compact Muon Solenoid(CMS)detector and to extend the Resistive Plate Chamber(RPC)system coverage,improved RPCs(iRPCs)with either orthogonal ...Purpose To complement and ensure redundancy in the endcap muon system of the Compact Muon Solenoid(CMS)detector and to extend the Resistive Plate Chamber(RPC)system coverage,improved RPCs(iRPCs)with either orthogonal layer strips with one-end electronics or single layer strips with two-end electronics providing more precise time measurement will be installed in the very forward pseudorapidity region of|η|<2.4.The iRPC readout system needs to support twodimensional(2D)or two-end readout.In addition,it must combine detector data with Timing,Trigger and fast Control(TTC)and Slow Control(SC)into one data stream over a bi-directional optical link with a line rate of 4.8 Gb/s between the Front-End Electronics(FEE)and the Back-End Electronics(BEE).To fulfill these requirements,a prototype BEE for the iRPC 2D chamber has been researched and designed.Methods A Micro-Telecommunication and Computing Architecture(μTCA)-based processing card was designed in this study to establish a prototype system together with aμTCA crate.The Giga-Bit Transceiver(GBT)protocol is integrated to provide bi-directional communication between the FEE and BEE.A server is connected with the BEE by a Gigabit Ethernet(GbE)link for SC and a 10-GbE link for Data AcQuisition(DAQ).Results The Bit Error Rate(BER)test of the back-end board and a joint test with the iRPC 2D prototype chamber were performed.ABERof less than 1.331×10−16 was obtained.The timemeasurement with a resolution of 3.05 nswas successfully realized,and detector efficiencies of 97.7%for longitudinal strips and 96.0%for orthogonal strips were measured.Test results demonstrate the correctness and reliability of the prototype BEE.Conclusion The BEE prototype satisfies the requirements for the iRPC 2D chamber,and it worked stably and reliably during a long-term joint test run.展开更多
基金supported in part by the National Key R&D Program of China(No.2022YFA1602101)the National Natural Science Foundation of China(No.12035018)+26 种基金We would also like to acknowledge the enduring support for the CMS Phase-2 upgrade and the supporting computing infrastructure provided by the following funding agencies:FWO(Belgium)CNPq(Brazil),CAPES(Brazil)FAPERJ(Brazil)MES(Bulgaria)BNSF(Bulgaria)CERNCAS(China)MoST(China)MINCIENCIAS(Colombia)CEA(France)CNRS/IN2P3(France)SRNSFG(Georgia)[YS-21-1798]DAE(India)DST(India)IPM(Iran)INFN(Italy)MSIP(Republic of Korea)NRF(Republic of Korea)BUAP(Mexico)CINVESTAV(Mexico)CONACYT(Mexico)LNS(Mexico)SEP(Mexico)UASLP-FAI(Mexico)PAEC(Pakistan)DOE(USA)NSF(USA).
文摘Purpose Improved resistive plate chambers(iRPCs)will be installed in the challenging forward region of the compact muon solenoid(CMS)during its Phase-2 upgrade.The design target of iRPC time resolution is 1.5 ns.It will help the Level-1 trigger system distinguish the muons from high backgrounds and improve the trigger efficiency.Studying the time resolution after integrating the new backend electronics boards(BEB)is essential for ensuring timely performance.In this system,a time reference(Tref)signal is distributed by the BEB to several frontend electronics boards(FEB)to reset the time-to-digital converters(TDC).In the CMS experiment,the arrangement of the iRPC chambers and on-chamber FEBs is at different positions,resulting in varying Tref arrival times on the FEB side.This paper describes the measures taken to ensure the time resolution of the single path and adjust the time base for multi-paths.Method Unique designs were implemented in the chamber,FEB,and BEB to ensure a satisfactory time resolution.Tref adjustments for different paths were performed in bunch crossing steps(24.950 ns)in the BEB using shift registers.And the sub-bunch crossing adjustment steps were performed in the FEB using the TDC correction module.Finally,the arrival time differences of Tref on different FEBs were less than 1.25 ns after adjustment.Results The time resolution of the FEB–BEB system was observed to be 32 ps.The time resolution of the chamber FEB–BEB system was first measured and is 554 ps at an iRPC working point of 7200 V.In addition,the Tref arrival time differences of different paths were adjusted from−99.923(−90.113)ns to 0.073(−0.141)ns.Conclusion The test results revealed that the system time resolution and Tref adjustment performed by the BEB met the Phase-2 upgrade goals.
基金supported by the National Natural Science Foundation of China(No.12035018)the IHEP Innovation Fund(Y9545150U2)the National Key Programme for S&T Research and Development(Grant No.:2016YFA0400104).
文摘Purpose The Large Hadron Collider(LHC)at European Organization for Nuclear Research is planned to be upgraded to the high luminosity LHC.Increasing the luminosity makes muon triggering reliable and offline reconstruction very challenging.To enhance the redundancy of the Compact Muon Solenoid(CMS)Muon system and resolve the ambiguity of track reconstruction in the forward region,an improved Resistive Plate Chamber(iRPC)with excellent time resolution will be installed in the Phase-2 CMS upgrade.The iRPC will be equipped with Front-End Electronics(FEE),which can perform high-precision time measurements of signals from both ends of the strip.New Back-End Electronics(BEE)need to be researched and developed to provide sophisticated functionalities such as interacting with FEE with shared links for fast,slow control(SC)and data,in addition to trigger primitives(TPs)generation and data acquisition(DAQ).Method The BEE prototype uses a homemade hardware board compatible with the MTCA standard,the back-end board(BEB).BEE interacts with FEE via a bidirectional 4.8 Gbps optical paired-link that integrates clock,data,and control information.The clock and fast/slow control commands are distributed from BEB to the FEE via the downlink.The uplink is used for BEB to receive the time information of the iRPC’sfired strips and the responses to the fast/slow control commands.To have a pipelined detector data for clusterfinding operation,recover(DeMux)the time relationship of which is changed due to the transmission protocol for the continuous incoming MUXed data from FEE.Then at each bunch crossing(BX),clusteringfired strips that satisfy time and spatial constraints to generate TPs.Both incoming raw MUXed detector data and TPs in a time window and latency based on the trigger signal are read out to the DAQ system.Gigabit Ethernet(GbE)of SiTCP and commercial 10-GbE are used as link standards for SC and DAQ,respectively,for the BEB to interact with the server.Results The joint test results of the BEB with iRPC and Front-End Board(FEB)show a Bit Error Rate of the transmission links less than 1×10-16,a time resolution of the FEB Time-to-Digital Converter of 16 ps,and the resolution of the time difference between both ends of 160 ps which corresponding a spatial resolution of the iRPC of approximately 1.5 cm.Conclusion Test results showed the correctness and stable running of the BEB prototype,of which the functionalities fulfill the iRPC requirements.
基金the National Key Programme for S&T Research and Development(Grant NO.:2016YFA0400104)the National Natural Science Foundation of China(No.12035018)the IHEP Innovation Fund(Y9545150U2).
文摘Purpose To complement and ensure redundancy in the endcap muon system of the Compact Muon Solenoid(CMS)detector and to extend the Resistive Plate Chamber(RPC)system coverage,improved RPCs(iRPCs)with either orthogonal layer strips with one-end electronics or single layer strips with two-end electronics providing more precise time measurement will be installed in the very forward pseudorapidity region of|η|<2.4.The iRPC readout system needs to support twodimensional(2D)or two-end readout.In addition,it must combine detector data with Timing,Trigger and fast Control(TTC)and Slow Control(SC)into one data stream over a bi-directional optical link with a line rate of 4.8 Gb/s between the Front-End Electronics(FEE)and the Back-End Electronics(BEE).To fulfill these requirements,a prototype BEE for the iRPC 2D chamber has been researched and designed.Methods A Micro-Telecommunication and Computing Architecture(μTCA)-based processing card was designed in this study to establish a prototype system together with aμTCA crate.The Giga-Bit Transceiver(GBT)protocol is integrated to provide bi-directional communication between the FEE and BEE.A server is connected with the BEE by a Gigabit Ethernet(GbE)link for SC and a 10-GbE link for Data AcQuisition(DAQ).Results The Bit Error Rate(BER)test of the back-end board and a joint test with the iRPC 2D prototype chamber were performed.ABERof less than 1.331×10−16 was obtained.The timemeasurement with a resolution of 3.05 nswas successfully realized,and detector efficiencies of 97.7%for longitudinal strips and 96.0%for orthogonal strips were measured.Test results demonstrate the correctness and reliability of the prototype BEE.Conclusion The BEE prototype satisfies the requirements for the iRPC 2D chamber,and it worked stably and reliably during a long-term joint test run.
